Benjamin D. Parker

According to our database1, Benjamin D. Parker authored at least 28 papers between 1995 and 2018.

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Bibliography

2018
A High-Resolution Minimicroscope System for Wireless Real-Time Monitoring.
IEEE Trans. Biomed. Eng., 2018

2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks.
IEEE J. Solid State Circuits, 2015

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits.
IEEE Des. Test, 2014

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.
IEEE J. Solid State Circuits, 2013

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.
IEEE J. Solid State Circuits, 2013

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
IEEE J. Solid State Circuits, 2012

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012


2011
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2006
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
The Biomolecular Interaction Network Database and related tools 2005 update.
Nucleic Acids Res., 2005

2004
A semi-digital delay-locked loop using an analog-based finite state machine.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

2003
SiGe BiCMOS integrated circuits for high-speed serial communication links.
IBM J. Res. Dev., 2003

1998

1995
CMOS circuits for Gb/s serial data communication.
IBM J. Res. Dev., 1995


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