Benjamin D. Parker
According to our database1,
Benjamin D. Parker
authored at least 32 papers
between 1995 and 2018.
Collaborative distances:
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Bibliography
2018
IEEE Trans. Biomed. Eng., 2018
2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
IEEE J. Solid State Circuits, 2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Des. Test, 2014
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing".
IEEE J. Solid State Circuits, June, 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
IEEE J. Solid State Circuits, 2012
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2009
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
Nucleic Acids Res., 2005
IEEE J. Solid State Circuits, 2005
2004
IEEE Trans. Circuits Syst. II Express Briefs, 2004
2003
IBM J. Res. Dev., 2003
2000
SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems.
IEEE J. Solid State Circuits, 2000
1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
1995