Mario Kovac

According to our database1, Mario Kovac authored at least 23 papers between 1992 and 2019.

Collaborative distances:



In proceedings 
PhD thesis 




An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator.
Proceedings of the Parallel Processing and Applied Mathematics, 2019

Bolt65 - performance-optimized HEVC HW/SW suite for Just-in-Time video processing.
Proceedings of the 42nd International Convention on Information and Communication Technology, 2019

European processor initiative: the industrial cornerstone of EuroHPC for exascale era.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

Exploring manycore architectures for next-generation HPC systems through the MANGO approach.
Microprocess. Microsystems, 2018

Online efficient bio-medical video transcoding on MPSoCs through content-aware workload allocation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Thermal characterization of next-generation workloads on heterogeneous MPSoCs.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration.
Proceedings of the Parallel Computing is Everywhere, 2017

Enabling HPC for QoS-sensitive applications: The MANGO approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Work in progress: Embedded computer engineering learning platform capabilities.
Proceedings of the IEEE Global Engineering Education Conference, 2015

The MANGO FET-HPC Project: An Overview.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

E-Health Demystified: An E-Government Showcase.
Computer, 2014

Computer Engineering Laboratory Course: E2LP Platform Experience.
Proceedings of the 2014 Embedded Engineering Learning Platform Workshop, 2014

Unified, multiple target, computer engineering learning platform.
Proceedings of the 2014 IEEE Global Engineering Education Conference, 2014

Power consumption and bandwidth savings with video transcoding to mobile device-specific spatial resolution.
Proceedings of the 9th International Symposium on Communication Systems, 2014

Application of Dynamically Reconfigurable Processors in Digital Signal Processing.
Proceedings of the SIGMAP 2006, 2006

Universal Strong Encryption FPGA Core Implementation.
Proceedings of the 1998 Design, 1998

JAGUAR: a high speed VLSI chip for JPEG image compression standard.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A prototype VLSI chip architecture for JPEG image compression.
Proceedings of the 1995 European Design and Test Conference, 1995

ACE: A VLSI Chip for Galois Field GF (2<sup>m</sup>) Based Exponentiation.
Proceedings of the Seventh International Conference on VLSI Design, 1994

SIGMA: a VLSI systolic array implementation of a Galois field GF(2 <sup>m</sup>) based multiplication and division algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 1993

SIGMA: A VLSI Chip for Galois Field GF(2<sup>m</sup>) Based Multiplication and Division.
Proceedings of the Sixth International Conference on VLSI Design, 1993

A Systolic Algorithm and Architecture for Galois Field Arithmetic.
Proceedings of the 6th International Parallel Processing Symposium, 1992