Yosinori Watanabe

According to our database, Yosinori Watanabe authored at least 57 papers between 1991 and 2017.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2017

Hardware/Software Codesign Across Many Cadence Technologies.

Grant Martin, Frank Schirrmeister, Yosinori Watanabe

Proceedings of the Handbook of Hardware/Software Codesign., 2017

2013

Share with care: a quantitative evaluation of sharing approaches in high-level synthesis.

Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Clearing the clutter: Unified modeling and verification methodology for system level hardware design.

Yosinori Watanabe, Stuart Swan

Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Exploiting area/delay tradeoffs in high-level synthesis.

Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Realistic performance-constrained pipelining in high-level synthesis.

Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques.

Gianpiero Cabodi, Luciano Lavagno, Marco Murciano, Alex Kondratyev, Yosinori Watanabe

ACM Trans. Design Autom. Electr. Syst., 2010

Incremental high-level synthesis.

Luciano Lavagno, Alex Kondratyev, Yosinori Watanabe, Qiang Zhu, Mototsugu Fujii, Mitsuru Tatesawa, Noriyasu Nakayama

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Runtime deadlock analysis for system level design.

Eric Cheung, Xi Chen, Harry Hsieh, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe

Des. Autom. Embed. Syst., 2009

Examining Important Corner Cases: Verification of Interacting Architectural Components in System Designs.

Yosinori Watanabe

Proceedings of the Ninth International Conference on Application of Concurrency to System Design, 2009

2006

Schedulability Analysis of Petri Nets Based on Structural Properties.

Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli, Jörg Desel

Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

Functional Model Exploration for Multimedia Applications via Algebraic Operators.

Shinjiro Kakita, Yosinori Watanabe, Douglas Densmore, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

2005

Quasi-Static Scheduling of Concurrent Specifications.

Luciano Lavagno, Claudio Passerone, Alex Kondratyev, Yosinori Watanabe

Proceedings of the Embedded Systems Handbook., 2005

Eliminating false positives in crosstalk noise analysis.

Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Quasi-static scheduling of independent tasks for reactive systems.

Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A BMC-based formulation for the scheduling problem of hardware systems.

Gianpiero Cabodi, Alex Kondratyev, Luciano Lavagno, Sergio Nocco, Stefano Quer, Yosinori Watanabe

Int. J. Softw. Tools Technol. Transf., 2005

A structural approach to quasi-static schedulability analysis of communicating concurrent programs.

Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli

Proceedings of the EMSOFT 2005, 2005

A Time Slice Based Scheduler Model for System Level Design.

Luciano Lavagno, Claudio Passerone, Vishal Shah, Yosinori Watanabe

Proceedings of the 2005 Design, 2005

Simulation based deadlock analysis for system level designs.

Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe

Proceedings of the 42nd Design Automation Conference, 2005

2004

Logic of constraints: a quantitative performance and functional constraint formalism.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Quasi-static Scheduling for Concurrent Architectures.

Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Yosinori Watanabe

Fundam. Informaticae, 2004

Separation of concerns: overhead in modeling and efficient simulation techniques.

Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin

Proceedings of the EMSOFT 2004, 2004

Eliminating False Positives in Crosstalk Noise Analysis.

Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska

Proceedings of the 2004 Design, 2004

2003

A BMC-formulation for the scheduling problem in highly constrained hardware Systems.

Gianpiero Cabodi, Sergio Nocco, Stefano Quer, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe

Proceedings of the First International Workshop on Bounded Model Checking, 2003

Formal Verification for Embedded System Designs.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Des. Autom. Embed. Syst., 2003

Metropolis: An Integrated Electronic System Design Environment.

Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli

Computer, 2003

Verifying LOC based functional and performance constraints.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling.

Antonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev

Proceedings of the 2003 Design, 2003

Automatic Generation of Simulation Monitors from Quantitative Constraint Formula.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the 2003 Design, 2003

Gain-based technology mapping for discrete-size cell libraries.

Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska

Proceedings of the 40th Design Automation Conference, 2003

Automatic trace analysis for logic of constraints.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the 40th Design Automation Conference, 2003

Temporofunctional crosstalk noise analysis.

Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska

Proceedings of the 40th Design Automation Conference, 2003

Quasi-Static Scheduling for Concurrent Architectures.

Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe

Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

Case Studies of Model Checking for Embedded System Designs.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

State Space Compression in History Driven Quasi-Static Scheduling.

Antonio G. Lomeña, Marisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev

Proceedings of the Embedded Software for SoC, 2003

Simulation Trace Verification for Quantitative Constraints.

Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the Embedded Software for SoC, 2003

2002

Formal verification of embedded system designs at multiple levels of abstraction.

Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis.

Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe

Proceedings of the Embedded Software, Second International Conference, 2002

False Path Elimination in Quasi-Static Scheduling.

G. Arrigoni, L. Duchini, Claudio Passerone, Luciano Lavagno, Yosinori Watanabe

Proceedings of the 2002 Design, 2002

Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model.

Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Quasi-Static Scheduling of Independent Tasksfor Reactive Systems.

Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe

Proceedings of the Applications and Theory of Petri Nets 2002, 2002

Modeling and Designing Heterogeneous Systems.

Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe

Proceedings of the Concurrency and Hardware Design, Advances in Petri Nets, 2002

2001

Constraints specification at higher levels of abstraction.

Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Generation of minimal size code for scheduling graphs.

Claudio Passerone, Yosinori Watanabe, Luciano Lavagno

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Area and search space control for technology mapping.

Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten

Proceedings of the 37th Conference on Design Automation, 2000

Task generation and compile-time scheduling for mixed data-control embedded software.

Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 37th Conference on Design Automation, 2000

1999

Designing digital video systems: modeling and scheduling.

H. J. H. N. Kenter, Claudio Passerone, W. J. M. Smits, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

Quasi-Static Scheduling of Embedded Software Using Equal Conflict Nets.

Marco Sgroi, Luciano Lavagno, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Application and Theory of Petri Nets 1999, 1999

1996

Permissible functions for multioutput components in combinational logic optimization.

Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Logic decomposition during technology mapping.

Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

A delay model for logic synthesis of continuously-sized networks.

Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinori Watanabe

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

State Minimization of Pseudo Non-Deterministic FSM's.

Yosinori Watanabe, Robert K. Brayton

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Heuristic minimization of multiple-valued relations.

Yosinori Watanabe, Robert K. Brayton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Logic Optimization with Multi-Output Gates.

Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Heuristic Minimization of Synchronous Relations.

Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

The maximum set of permissible behaviors for FSM networks.

Yosinori Watanabe, Robert K. Brayton

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1991

Incremental Synthesis for Engineering Changes.

Yosinori Watanabe, Robert K. Brayton

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Heuristic Minimazation of Multiple-Valued Relations.

Yosinori Watanabe, Robert K. Brayton

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991