Alessandro De Gloria

Fabrizio Bracco

Proceedings of the WEBIST 2007, 2007

2005

COMUNICAR: designing a multimedia, context-aware human-machine interface for cars.

[BibT_eX]

[DOI]

Cogn. Technol. Work., 2005

Discovering the European Heritage Through the ChiKho Educational Web Game.

[BibT_eX]

[DOI]

Edmondo Ferretti

Proceedings of the Intelligent Technologies for Interactive Entertainment, 2005

2004

Evaluation and optimization of method calls in Java.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2004

Designing configurable automotive dashboards on liquid crystal displays.

[BibT_eX]

[DOI]

Cogn. Technol. Work., 2004

2003

VeGame: Exploring Art and History in Venice.

[BibT_eX]

[DOI]

Computer, 2003

MADE: developing edutainment applications on mobile computers.

[BibT_eX]

[DOI]

Comput. Graph., 2003

Supporting Efficient Design of Mobile HCI.

[BibT_eX]

[DOI]

Proceedings of the Human-Computer Interaction with Mobile Devices and Services, 2003

Designing Mobile Games for a Challenging Experience of the Urban Heritage.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002

Using 3D Sound to Improve the Effectiveness of the Advanced Driver Assistance Systems.

[BibT_eX]

[DOI]

Pers. Ubiquitous Comput., 2002

User Testing a Hypermedia Tour Guide.

[BibT_eX]

[DOI]

IEEE Pervasive Comput., 2002

IEEE Pervasive Computing: Integrated Environments - User Testing a Hypermedia Tour Guide.

[BibT_eX]

IEEE Distributed Syst. Online, 2002

2001

DirectJ: Java APIs for optimized 2D graphics.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2001

JSBricks: a suite of microbenchmarks for the evaluation of Java as a scientific execution environment.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2001

WLESS-frame: a simulation-based development environment for 802.11 stations.

[BibT_eX]

[DOI]

Comput. Networks, 2001

AutoGraL: a Java 2D graphics library for configurable automotive dashboards.

[BibT_eX]

[DOI]

Marco Risso

Alessandro Villamaina

Comput. Graph., 2001

An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

IP cell for error correction systems in Minidisc.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2000

Semicustom Design of an IEEE 1394-Compliant Reusable IC Core.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2000

Invocation profile characterization of Java applications.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000

1999

Microprocessor design for embedded system.

[BibT_eX]

[DOI]

J. Syst. Archit., 1999

A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications.

[BibT_eX]

[DOI]

Alessandro Trifiletti

Proceedings of the IEEE International Conference On Computer Design, 1999

Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications.

[BibT_eX]

[DOI]

Paolo Palma

Proceedings of the 25th EUROMICRO '99 Conference, 1999

1997

Design of an ASIP architecture for low-level visual elaborations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1997

Fuzzy logic microcontroller.

[BibT_eX]

[DOI]

IEEE Micro, 1997

Parallel VLSI Architectures for Cryptographic Systems.

[BibT_eX]

[DOI]

Fabio Ancona

Rodolfo Zunino

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1996

An asynchronous distributed architecture model for the Boltzmann machine control mechanism.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1996

Hardware design of asynchronous fuzzy controllers.

[BibT_eX]

[DOI]

Alessandra Costa

IEEE Trans. Fuzzy Syst., 1996

Statistical Carry Lookahead Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

1995

Efficient semicustom micropipeline design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1995

Hardware solutions for fuzzy control.

[BibT_eX]

[DOI]

Proc. IEEE, 1995

1994

Block placement with a Boltzmann Machine.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

An evaluation system for distributed-time VHDL simulation.

[BibT_eX]

[DOI]

Proceedings of the Eighth Workshop on Parallel and Distributed Simulation, 1994

1993

Efficient implementation of the Boltzmann machine algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1993

Clustered Boltzmann Machines: Massively Parallel Architectures for Constrained Optimization Problems.

[BibT_eX]

[DOI]

Parallel Comput., 1993

Delay insensitive micro-pipelined combinational logic.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

Design of a massively parallel SIMD architecture for the Boltzmann machine.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

A delay insensitive approach to the VLSI design of a DRAM controller.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

A parallel architecture for the Color Doppler flow technique in ultrasound imaging.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

An asynchronous approach to the RISC design of a micro-controller.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

An analysis of dynamic scheduling techniques for symbolic applications.

[BibT_eX]

[DOI]

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1992

A dedicated massively parallel architecture for the Boltzmann machine.

[BibT_eX]

[DOI]

Sandro Ridella

Parallel Comput., 1992

Massive parallelism in multi-level simulation of VLSI circuits.

[BibT_eX]

[DOI]

Integr., 1992

A non-deterministic scheduler for a software pipelining compiler.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Instruction-level Parallelism in Prolog: Analysis and Architectural Support.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1991

A Boltzmann Machine approach to code optimization.

[BibT_eX]

[DOI]

Parallel Comput., 1991

1990

VISA: A variable instruction set architecture.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 1990

An evaluation system for application specific architectures.

[BibT_eX]

[DOI]