Bogdan Pasca

According to our database1, Bogdan Pasca authored at least 35 papers between 2008 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Extracting INT8 Multipliers from INT18 Multipliers.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

High Precision, High Performance FPGA Adders.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Hybrid Dot-Product Design for FP-Enabled FPGAs.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018
Activation Function Architectures for FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

High-Performance QR Decomposition for FPGAs.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
Single Precision Logarithm and Exponential Architectures for Hard Floating-Point Enabled FPGAs.
IEEE Trans. Computers, 2017

Model-based hardware design based on compatible sets of isomorphic subgraphs.
Proceedings of the International Conference on Field Programmable Technology, 2017

Floating Point Tangent Implementation for FPGAs.
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

Flexible Fixed-Point Function Generation for FPGAs.
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

2016
Single Precision Natural Logarithm Architecture for Hard Floating-Point and DSP-Enabled FPGAs.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2015
High-Level Design Tools for Floating Point FPGAs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Floating-Point DSP Block Architecture for FPGAs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Design and Implementation of an Embedded FPGA Floating Point DSP Block.
Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015

2014
Tools and Techniques for Efficient High-Level System Design on FPGAs.
CoRR, 2014

Low-cost multiplier-based FPU for embedded processing on FPGA.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Floating-Point Exponentiation Units for Reconfigurable Computing.
TRETS, 2013

Efficient floating-point polynomial evaluation on FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Faithful single-precision floating-point tangent for FPGAs.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Elementary Function Implementation with Optimized Sub Range Polynomial Evaluation.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
FPGA-specific synthesis of loop-nests with pipelined computational cores.
Microprocessors and Microsystems - Embedded Hardware Design, 2012

Correctly rounded floating-point division for DSP-enabled FPGAs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
Designing Custom Arithmetic Data Paths with FloPoCo.
IEEE Design & Test of Computers, 2011

FPGA-Specific Arithmetic Optimizations of Short-Latency Adders.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

An FPGA architecture for solving the Table Maker's Dilemma.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

Automatic Generation of FPGA-Specific Pipelined Accelerators.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Multipliers for floating-point double precision and beyond on FPGAs.
SIGARCH Computer Architecture News, 2010

Floating-point exponential functions for DSP-enabled FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Pipelined FPGA Adders.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Multiplicative Square Root Algorithms for FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Automatic generation of polynomial-based hardware architectures for function evaluation.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Large multipliers with fewer DSP blocks.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Generating high-performance custom floating-point pipelines.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
An FPGA-specific approach to floating-point accumulation and sum-of-products.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008


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