Valery A. Vardanian

According to our database1, Valery A. Vardanian authored at least 33 papers between 1985 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
On a Method for Segmentation of Memory Instances with Row Redundancies.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

2015
An efficient approach for memory repair by reducing the number of spares.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2014
Fault modeling and test algorithm creation strategy for FinFET-based memories.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Extending fault periodicity table for testing faults in memories under 20nm.
Proceedings of the 2014 East-West Design & Test Symposium, 2014

2013
An effective solution for building memory BIST infrastructure based on fault periodicity.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters.
Proceedings of the East-West Design & Test Symposium, 2013

Impact of process variations on read failures in SRAMs.
Proceedings of the East-West Design & Test Symposium, 2013

Application of defect injection flow for fault validation in memories.
Proceedings of the East-West Design & Test Symposium, 2013

2012
A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
Symmetry Measure for Memory Test and Its Application in BIST Optimization.
J. Electron. Test., 2011

Generic BIST architecture for testing of content addressable memories.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A Robust Solution for Embedded Memory Test and Repair.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
An efficient March test for detection of all two-operation dynamic faults from subclass Sav.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

2008
An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2007
Minimal March Tests for Detection of Dynamic Faults in Random Access Memories.
J. Electron. Test., 2007

A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A March-Based Algorithm for Location and Full Diagnosis of All Unlinked Static Faults.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

Minimal March Tests for Dynamic Faults in Random Access Memories.
Proceedings of the 11th European Test Symposium, 2006

Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
Minimal March Tests for Unlinked Static Faults in Random Access Memories.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Impact of Soft Error Challenge on SoC Design.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2004
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure.
IEEE Des. Test Comput., 2004

A Methodology for Design and Evaluation of Redundancy Allocation Algorithms.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Embedded Memory Reliability: The SER Challenge.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

2002
A March-Based Fault Location Algorithm for Static Random Access Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

2001
An Approach for Evaluation of Redunancy Analysis Algorithms.
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

2000
Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check.
Proceedings of the 2000 Design, 2000

1997
Exact probabilistic analysis of error detection for parity checkers.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

1996
On completely robust path delay fault testable realization of logic functions.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1994
On the Complexity of Dynamic Tests for Logic Functions.
Acta Cybern., 1994

On the complexity of terminal stuck-at fault detection tests for monotone Boolean functions.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

1985
On the length of single dynamic tests for monotone Boolean functions.
Proceedings of the Fundamentals of Computation Theory, 1985


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