Alessio Spessot

Orcid: 0000-0003-2381-0121

According to our database1, Alessio Spessot authored at least 21 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2022
Multitimescale Mitigation for Performance Variability Improvement in Time-Critical Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2022

High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations.
Proceedings of the IEEE International Memory Workshop, 2022

Proactive Run-Time Mitigation for Time-Critical Applications Using Dynamic Scenario Methodology.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020
Fast & Accurate Methodology for Aging Incorporation in Circuits using Adaptive Waveform Splitting (AWS).
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Device Scaling roadmap and its implications for Logic and Analog platform.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2020

2019
Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2017
SRAM designs for 5nm node and beyond: Opportunities and challenges.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2015
Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Assessment of SiGe quantum well transistors for DRAM peripheral applications.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Off-state stress degradation mechanism on advanced p-MOSFETs.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014
Impact of Off State Stress on advanced high-K metal gate NMOSFETs.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012


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