Jürgen Bömmels

According to our database1, Jürgen Bömmels authored at least 14 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
3D SRAM Macro Design in 3D Nanofabric Process Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

Integration of a Stacked Contact MOL for Monolithic CFET.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2020
3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs.
Proceedings of the VLSI-SoC: Design Trends, 2020

Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

2017
Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects.
Microelectron. Reliab., 2017

2016
Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation.
Microelectron. Reliab., 2016

Evaluation of via density and low-k Young's modulus influence on mechanical performance of advanced node multi-level Back-End-Of-Line.
Microelectron. Reliab., 2016

2015
Constant voltage electromigration for advanced BEOL copper interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Intrinsic reliability of local interconnects for N7 and beyond.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Impact of process variability on BEOL TDDB lifetime model assessment.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability.
Microelectron. Reliab., 2014

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014



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