Rei Ueno

IACR Cryptol. ePrint Arch., 2024

2023

Side-Channel Analysis Against SecOC-Compliant AES-CMAC.

[BibT_eX]

[DOI]

Katsumi Ebina

IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

Homomorphic encryption for stochastic computing.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., June, 2023

How Secure is Exponent-blinded RSA-CRT with Sliding Window Exponentiation?

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Multiple-Valued Plaintext-Checking Side-Channel Attacks on Post-Quantum KEMs.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Crystalor: Persistent Memory Encryption Mechanism with Optimized Metadata Structure and Fast Crash Recovery.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2023

Formal Analysis of Non-profiled Deep-learning Based Side-channel Attacks.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2023

Efficient DFA-Resistant AES Hardware Based on Concurrent Fault Detection Scheme.

[BibT_eX]

[DOI]

Yusuke Yagyu

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

2022

ELM: A Low-Latency and Scalable Memory Encryption Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2022

Curse of Re-encryption: A Generic Power/EM Analysis on Post-Quantum KEMs.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

One Truth Prevails: A Deep-learning Based Single-Trace Power Analysis on RSA-CRT with Windowed Exponentiation.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Bypassing Isolated Execution on RISC-V using Side-Channel-Assisted Fault-Injection and Its Countermeasure.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Perceived Information Revisited New Metrics to Evaluate Success Rate of Side-Channel Attacks.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

AES S-Box Hardware With Efficiency Improvement Based on Linear Mapping Optimization.

[BibT_eX]

[DOI]

Ayano Nakashima

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

On the Success Rate of Side-Channel Attacks on Masked Implementations: Information-Theoretical Bounds and Their Practical Usage.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

SCARF: A Low-Latency Block Cipher for Secure Cache-Randomization.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

High-Speed Hardware Architecture for Post-Quantum Diffie-Hellman Key Exchange Based on Residue Number System.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Efficient Modular Polynomial Multiplier for NTT Accelerator of Crystals-Kyber.

[BibT_eX]

[DOI]

Yuma Itabashi

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021

Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2021

Imbalanced Data Problems in Deep Learning-Based Side-Channel Attacks: Analysis and Solution.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2021

A method for constructing sliding windows leak from noisy cache timing information.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2021

An Algebraic Approach to Verifying Galois-Field Arithmetic Circuits with Multiple-Valued Characteristics.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2021

Fault-Injection Attacks against NIST's Post-Quantum Cryptography Round 3 KEM Candidates.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2021

Toward Optimal Deep-Learning Based Side-Channel Attacks: Probability Concentration Inequality Loss and Its Usage.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2021

A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

A Formal Approach to Identifying Hardware Trojans in Cryptographic Hardware.

[BibT_eX]

[DOI]

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

2020

Rejection Sampling Schemes for Extracting Uniform Distribution from Biased PUFs.

[BibT_eX]

[DOI]

Kohei Kazumori

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Unified Hardware for High-Throughput AES-Based Authenticated Encryptions.

[BibT_eX]

[DOI]

Shotaro Sawataishi

IEEE Trans. Circuits Syst. II Express Briefs, 2020

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Bypassing Isolated Execution on RISC-V with Fault Injection.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Debiasing Method for Efficient Ternary Fuzzy Extractors and Ternary Physically Unclonable Functions.

[BibT_eX]

[DOI]

Kohei Kazumori

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Effective Formal Verification for Galois-field Arithmetic Circuits with Multiple-Valued Characteristics.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

PMAC++: Incremental MAC Scheme Adaptable to Lightweight Block Ciphers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Single-Trace Side-Channel Analysis on Polynomial-Based MAC Schemes.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020

Practical Side-Channel Based Model Extraction Attack on Tree-Based Machine Learning Algorithm.

[BibT_eX]

[DOI]

Proceedings of the Applied Cryptography and Network Security Workshops, 2020

2019

Efficient Fuzzy Extractors Based on Ternary Debiasing Method for Biased Physically Unclonable Functions.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Tackling Biased PUFs Through Biased Masking: A Debiasing Method for Efficient Fuzzy Extractor.

[BibT_eX]

[DOI]

Manami Suzuki

IEEE Trans. Computers, 2019

Highly efficient GF(2<sup>8</sup>) inversion circuit based on hybrid GF representations.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2019

Constructing Sliding Windows Leak from Noisy Cache Timing Information of OSS-RSA.

[BibT_eX]

[DOI]

Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019

A Ternary Fuzzy Extractor for Efficient Cryptographic Key Generation.

[BibT_eX]

[DOI]

Kohei Kazumori

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

High Throughput/Gate FN-Based Hardware Architectures for AES-OTR.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Characterizing Parallel Multipliers for Detecting Hardware Trojans.

[BibT_eX]

[DOI]

FLAP, 2018

Quaternary Debiasing for Physically Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

On the Detectability of Hardware Trojans Embedded in Parallel Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

On Masked Galois-Field Multiplication for Authenticated Encryption Resistant to Side Channel Analysis.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2018

A Non-Reversible Insertion Method for Hardware Trojans Based on Path Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the PROOFS 2018, 2018

2017

Formal Approach for Verifying Galois Field Arithmetic Circuits of Higher Degrees.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Hierarchical Formal Verification Combining Algebraic Transformation with PPRM Expansion and Its Application to Masked Cryptographic Processors.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Automatic Generation System for Multiple-Valued Galois-Field Parallel Multipliers.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2017

A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares.

[BibT_eX]

[DOI]

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Practical Power Analysis on KCipher-2 Software on Low-End Microcontrollers.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE European Symposium on Security and Privacy Workshops, 2017

Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Toward More Efficient DPA-Resistant AES Hardware Architecture Based on Threshold Implementation.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017

Multiple-Valued Debiasing for Physically Unclonable Functions and Its Application to Fuzzy Extractors.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017

2016

A Formal Verification Method of Error Correction Code Processors Over Galois-Field Arithmetic.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2016

A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Formal Design of Pipelined GF Arithmetic Circuits and Its Application to Cryptographic Processors.

[BibT_eX]

[DOI]

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2015

Efficient DFA on SPN-Based Block Ciphers and Its Application to the LED Block Cipher.

[BibT_eX]

[DOI]