Junhua Liu
Orcid: 0000-0002-2492-8124Affiliations:
- Peking University, Beijing, China
According to our database1,
Junhua Liu
authored at least 35 papers
between 2009 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
DRGA-Based Second-Order Block Arnoldi Method for Model Order Reduction of MIMO RCS Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024
2023
A 2.85-mm<sup>2</sup> Wideband RF Transceiver in 40-nm CMOS for IoT Micro-Hub Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
Equiprobability-Based Local Response Surface Method for High-Sigma Yield Estimation With Both High Accuracy and Efficiency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
An All-Digital Outphasing Transmitter IC for Ka-Band Bit-to-RF Concurrent Multi-Beam DBF Array.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope.
IEEE J. Solid State Circuits, 2022
Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Towards the Characterization of Full ID-VG Degradation in Transistors for Future Analog Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
New Insight into the Aging Induced Retention Time Degraded of Advanced DRAM Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2021
32.5 A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs Slope.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A Hybrid Digital Transmitter Architecture for High- Efficiency and High-Speed Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Gm-Compensated 46-101 GHz Broadband Power Amplifier for High-Resolution FMCW Radars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 12-GHz Calibration-Free All-Digital PLL for FMCW Signal Generation With 78 MHz/μs Chirp Slope and High Chirp Linearity.
IEEE Trans. Circuits Syst., 2020
A 0.5-V 3.69-nW Complementary Source-Follower-C Based Low-Pass Filter for Wearable Biomedical Applications.
IEEE Trans. Circuits Syst., 2020
An 81-99 GHz Tripler with Fundamental Cancellation and 3rd Harmonic Enhancement Technique in 40-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 2.9 GHz Variable Inductor-Based DCO With 1.3 kHz Frequency Resolution for FMCW Radar Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 28 GHz 8-Bit Calibration-Free LO-Path Phase Shifter using Transformer-Based Vector Summing Topology in 40 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Calibration-Free Fractional-N ADPLL using Retiming Architecture and a 9-bit 0.3ps-INL Phase Interpolator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 12-GHz All-Digital Calibration-Free FMCW Signal Generator Based on a Retiming Fractional Frequency Divider.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
A 2.4-mW interference-resilient receiver front end with series N-path filter-based balun for body channel communication.
Int. J. Circuit Theory Appl., 2018
A Digital Phase Noise Cancelling Scheme for Ring Oscillator-based Fractional-N ADPLL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 12-bit 2.5 GHz 0.37ps-Peak-INL Digital-to-Time Converter with Parasitic-Insensitive Charge-Based Phase Interpolator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 43.2 μW 2.4 GHz 64-QAM Pseudo-Backscatter Modulator Based on Integrated Directional Coupler.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A low-power calibration-free fractional-N digital PLL with high linear phase interpolator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A high frequency resolution digitally controlled oscillator with differential tapped inductor.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A power efficient 1.0625-3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications.
Sci. China Inf. Sci., 2014
2013
Sci. China Inf. Sci., 2013
2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009