Kuan-Yu Chen
Orcid: 0000-0002-4168-6446Affiliations:
- University of Michigan, Department of Electrical Engineering and Computer Science, Ann Arbor, MI, USA (PhD 2024)
- Tenstorrent USA, Inc., Austin, TX, USA
According to our database1,
Kuan-Yu Chen
authored at least 21 papers
between 2019 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis.
Commun. ACM, May, 2025
DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET.
IEEE J. Solid State Circuits, February, 2025
Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025
2024
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication.
ACM Trans. Reconfigurable Technol. Syst., December, 2024
IEEE Des. Test, February, 2024
ParaBase: A Configurable Parallel Baseband Processor for Ultra-High-Speed Inter-Satellite Optical Communications.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
Proceedings of the 25th Annual Conference of the International Speech Communication Association, 2024
2022
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.
IEEE J. Solid State Circuits, 2022
A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
A Long-Range Narrowband RF Localization System with a Crystal-Less Frequency-Hopping Receiver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Squaring the circle: Executing Sparse Matrix Computations on FlexTPU - A TPU-Like Processor.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022
Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022
2021
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
2020
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits, 2020
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020
2019
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019