Lei Yang
Orcid: 0000-0002-0646-440XAffiliations:
- University of Notre Dame, Department of Computer Science and Engineering, IN, USA
- University of Pittsburgh, Department of Electrical and Computer Engineering, PA, USA
- Chongqing University, College of Computer Science, China
According to our database1,
Lei Yang
authored at least 59 papers
between 2014 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on ics.uci.edu
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on orcid.org
On csauthors.net:
Bibliography
2023
Hardware-aware neural architecture search for stochastic computing-based neural networks on tiny devices.
J. Syst. Archit., February, 2023
Muffin: A Framework Toward Multi-Dimension AI Fairness by Uniting Off-the-Shelf Models.
CoRR, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
J. Imaging, December, 2022
Development of A Real-time POCUS Image Quality Assessment and Acquisition Guidance System.
CoRR, 2022
Federated Self-Supervised Contrastive Learning and Masked Autoencoder for Dermatological Disease Diagnosis.
CoRR, 2022
Federated Contrastive Learning for Dermatological Disease Diagnosis via On-device Learning.
CoRR, 2022
CoRR, 2022
Hardware-aware Automated Architecture Search for Brain-inspired Hyperdimensional Computing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
On the Design of Minimal-Cost Pipeline Systems Satisfying Hard/Soft Real-Time Constraints.
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators.
IEEE Trans. Computers, 2021
Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlow.
CoRR, 2021
Federated Contrastive Learning for Dermatological Disease Diagnosis via On-device Learning (Invited Paper).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
FL-DISCO: Federated Generative Adversarial Network for Graph-based Molecule Drug Discovery: Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlow (Invited Paper).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search With Hot Start.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Co-Exploring Neural Architecture and Network-on-Chip Design for Real-Time Artificial Intelligence.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
ACM Trans. Embed. Comput. Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router.
IEEE Trans. Computers, 2019
XFER: A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AI.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Routing in optical network-on-chip: minimizing contention with guaranteed thermal reliability.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip.
IEEE Trans. Computers, 2018
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018
User Experience-Enhanced and Energy-Efficient Task Scheduling on Heterogeneous Multi-Core Mobile Systems.
Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018
On the Design of Reliable Heterogeneous Systems via Checkpoint Placement and Core Assignment.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Communication optimization for thermal reliable optical network-on-chip: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018
2017
Optimal Functional-Unit Assignment for Heterogeneous Systems Under Timing Constraint.
IEEE Trans. Parallel Distributed Syst., 2017
FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era.
IEEE Trans. Parallel Distributed Syst., 2017
Future Gener. Comput. Syst., 2017
Fixed priority scheduling of real-time flows with arbitrary deadlines on smart NoCs: work-in-progress.
Proceedings of the Thirteenth ACM International Conference on Embedded Software 2017 Companion, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Properties of Self-Timed Ring Architectures for Deadlock-Free and Consistent Configuration Reaching Maximum Throughput.
J. Signal Process. Syst., 2016
Application Mapping and Scheduling for Network-on-Chip-Based Multiprocessor System-on-Chip With Fine-Grain Communication Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2016
FoToNoC: A hierarchical management strategy based on folded lorus-like Network-on-Chip for dark silicon many-core systems.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
De-Frag: an efficient scheme to improve deduplication performance via reducing data placement de-linearization.
Clust. Comput., 2015
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015
Traffic-Aware Application Mapping for Network-on-Chip Based Multiprocessor System-on-Chip.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
On the Design of High-Performance and Energy-Efficient Probabilistic Self-Timed Systems.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
An Efficient Technique for Chip Temperature Optimization of Multiprocessor Systems in the Dark Silicon Era.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
2014
Contention-aware task and communication co-scheduling for network-on-chip based Multiprocessor System-on-Chip.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014
An Improved Thermal Model for Static Optimization of Application Mapping and Scheduling in Multiprocessor System-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014