Lu Jie
Orcid: 0000-0001-5046-3917Affiliations:
- Tsinghua University, Department of Electronic Engineering, Beijing, China
- University of Michigan, Department of Electrical and Computer Engineering, Ann Arbor, MI, USA (PhD 2021)
- Zhejiang University, Hangzhou, Zhejiang, China (former)
According to our database1,
Lu Jie
authored at least 43 papers
between 2017 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing.
IEEE J. Solid State Circuits, August, 2025
IEEE Trans. Circuits Syst. II Express Briefs, May, 2025
A 1-GS/s 11-b Time-Interleaved SAR ADC With Robust, Fast, and Accurate Autocorrelation-Based Background Timing-Skew Calibration.
IEEE J. Solid State Circuits, February, 2025
3.4: A CMOS Operational Amplifier Achieving ±5.8µV 3σ Offset and ±88nV/°C 3σ Offset Drift Using an on-Chip Heater-Based Self-Trimming Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with Concurrent Residue Transfer and Quantization, and Automatic Buffer Power Gating.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
24.1 A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
A Hierarchical Compilation Method for Programmable Analog-to-Digital Converter Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
A 75-MHz-BW 3rd-order Time-Interleaved Noise-Shaping SAR ADC with Shared EF-CIFF Loop Filter and Ring Buffer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
A 0.16mm<sup>2</sup>450MHz-BW 72dB-SNDR Continuous-time Pipeline ADC with APF+HPF and APF+FIR Hybrid Delay Alignment Techniques.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
A Power-Efficient Jitter-Insensitive 3.2GHz 1-bit CT ΔΣ ADC with Direct Charge Dump Feedback.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
A 0.004-mm<sup>2</sup> 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp.
IEEE J. Solid State Circuits, July, 2024
22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A Dithered-Digital-Mixing Background Timing-Skew Calibration Method for Time-Interleaved ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Conference on Integrated Circuits, 2024
A 1.2GS/s 11b Time-Interleaved SAR ADC with Low-Cost Derivative-Based Background Timing-Skew Calibration and Variable-Load Comparators.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor.
IEEE J. Solid State Circuits, December, 2023
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 0.021mm<sup>2</sup> 92dB-SNDR 88kHz-BW Incremental Zoom ADC with 2<sup>nd</sup>-order RT-DEM and Quiet Chopping.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 12b 1GS/s Pipelined ADC with Digital Background Calibration of Inter-stage Gain, Capacitor Mismatch, and Kick-back Errors.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 3.7mW 11b 1GS/s Time-Interleaved SAR ADC with Robust One-Stage Correlation-Based Background Timing-Skew Calibration.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 0.004mm<sup>2</sup> 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 0.014mm<sup>2</sup> 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Fast Converging Correlation-Based Background Timing Skew Calibration Technique by Digital Windowing for Time-Interleaved ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 0.37mm<sup>2</sup> 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2<sup>nd</sup>-order Vector-Quantizer DEM.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM.
IEEE J. Solid State Circuits, 2021
10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
IEEE J. Solid State Circuits, 2020
9.4 A 4<sup>th</sup>-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
IEEE J. Solid State Circuits, 2019
A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4<sup>th</sup>-Order Noise-Shaping SAR ADC.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2017
Sci. China Inf. Sci., 2017