Marco Antonio Zanata Alves

According to our database1, Marco Antonio Zanata Alves authored at least 49 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A Technologically Agnostic Framework for Cyber-Physical and IoT Processing-in-Memory-based Systems Simulation.
Microprocessors and Microsystems - Embedded Hardware Design, 2019

Towards providing middleware-level proactive resource reorganisation for elastic HPC applications in the cloud.
IJGUC, 2019

Trace-driven and processing time extensions for Noxim simulator.
Design Autom. for Emb. Sys., 2019

Skipping CNN Convolutions Through Efficient Memoization.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Multi-phased Task Placement of HPC Applications in the Cloud.
Proceedings of the 18th International Symposium on Parallel and Distributed Computing, 2019

Database Processing-in-Memory: A Vision.
Proceedings of the Database and Expert Systems Applications, 2019

A Compiler for Automatic Selection of Suitable Processing-in-Memory Instructions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018
Introducing Drowsy Technique to Cache Line Usage Predictors.
Proceedings of the Symposium on High Performance Computing Systems, 2018

Near-Data Filters: Taking Another Brick from the Memory Wall.
Proceedings of the International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2018

Evaluating Dead Line Predictors Efficiency with Drowsy Technique.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

Freezing Time: A New Approach for Emulating Fast Storage Devices Using VM.
Proceedings of the 26th IEEE International Symposium on Modeling, 2018

An Elastic Multi-Core Allocation Mechanism for Database Systems.
Proceedings of the 34th IEEE International Conference on Data Engineering, 2018

Exploring IoT platform with technologically agnostic processing-in-memory framework.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

HIPE: HMC instruction predication extension applied on database processing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Processing in 3D memories to speed up operations on complex data structures.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Design space exploration for PIM architectures in 3D-stacked memories.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
Affinity-Based Thread and Data Mapping in Shared Memory Systems.
ACM Comput. Surv., 2017

Trace-Driven Extension for Noxim Simulator.
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017

A generic processing in memory cycle accurate simulator under hybrid memory cube architecture.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Operand size reconfiguration for big data processing in memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Optimizing memory affinity with a hybrid compiler/OS approach.
Proceedings of the Computing Frontiers Conference, 2017

NIM: An HMC-Based Machine for Neuron Computation.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Kernel-Based Thread and Data Mapping for Improved Memory Affinity.
IEEE Trans. Parallel Distrib. Syst., 2016

A dynamic block-level execution profiler.
Parallel Computing, 2016

LAPT: A locality-aware page table for thread and data mapping.
Parallel Computing, 2016

Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Communication in Shared Memory: Concepts, Definitions, and Efficient Detection.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Large vector extensions inside the HMC.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Reconfigurable Vector Extensions inside the DRAM.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Opportunities and Challenges of Performing Vector Operations inside the DRAM.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

HMC and DDR Performance Trade-offs.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

SiNUCA: A Validated Micro-Architecture Simulator.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Locality and Balance for Communication-Aware Thread Mapping in Multicore Systems.
Proceedings of the Euro-Par 2015: Parallel Processing, 2015

Saving memory movements through vector processing in the DRAM.
Proceedings of the 2015 International Conference on Compilers, 2015

2014
Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols.
J. Parallel Distrib. Comput., 2014

Profiling and Reducing Micro-Architecture Bottlenecks at the Hardware Level.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Optimizing Memory Locality Using a Locality-Aware Page Table.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013
Energy Efficient Last Level Caches via Last Read/Write Prediction.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

2012
Memory-aware Thread and Data Mapping for Hierarchical Multi-core Platforms.
IJNC, 2012

Energy Savings via Dead Sub-Block Prediction.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

2011
High Latency and Contention on Shared L2-Cache for Many-Core Architectures.
Parallel Processing Letters, 2011

Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment.
Int. J. Reconfig. Comp., 2011

Using Memory Access Traces to Map Threads and Data on Hierarchical Multi-core Platforms.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
Impact of Parallel Workloads on NoC Architecture Design.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

TLP and ILP exploitation through a reconfigurable multiprocessor system.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Evaluating Thread Placement Based on Memory Access Patterns for Multi-core Processors.
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010

2009
Performance Evaluation of NoC Architectures for Parallel Workloads.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Design of Interleaved Multithreading for Network Processors on Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009


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