Rafael Tornero

According to our database1, Rafael Tornero
  • authored at least 16 papers between 2008 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration.
Proceedings of the Parallel Computing is Everywhere, 2017


2016
Enabling HPC for QoS-sensitive applications: The MANGO approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Customizable Heterogeneous Acceleration for Tomorrow's High-Performance Computing.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2013
Acceleration of Communication-Aware Task Mapping Techniques through GPU Computing.
Proceedings of the 27th International Conference on Advanced Information Networking and Applications Workshops, 2013

2012
Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach.
J. UCS, 2012

A Topology-Independent Mapping Technique for Application-Specific Networks-on-Chip.
Computing and Informatics, 2012

Computing Real-Time Dynamic Origin/Destination Matrices from Vehicle-to-Infrastructure Messages Using a Multi-Agent System.
Proceedings of the Highlights on Practical Applications of Agents and Multi-Agent Systems, 2012

An Optimal Control Approach to Power Management for Multi-Voltage and Frequency Islands Multiprocessor Platforms under Highly Variable Workloads.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

A multi-agent system for obtaining dynamic origin/destination matrices on intelligent road networks.
Proceedings of the Euro-American Conference on Telematics and Information Systems, 2012

2011
A Communication-Driven Routing Technique for Application-Specific NoCs.
International Journal of Parallel Programming, 2011

2010
Improving topological mapping on NoCs.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2009
A multi-objective strategy for concurrent mapping and routing in networks on chip.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Distance Constrained Mapping to Support NoC Platforms Based on Source Routing.
Proceedings of the Euro-Par 2009, 2009

2008
A Communication-Aware Topological Mapping Technique for NoCs.
Proceedings of the Euro-Par 2008, 2008

CART: Communication-Aware Routing Technique for Application-Specific NoCs.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008


  Loading...