Peter W. Cook

According to our database, Peter W. Cook authored at least 12 papers between 1984 and 2003.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2003

Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz.

Stanley Schuster, Peter W. Cook

IEEE J. Solid State Circuits, 2003

Dynamically Tuning Processor Resources with Adaptive Processing.

David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster

Computer, 2003

New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology.

Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology.

Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown

Proceedings of the ESSCIRC 2003, 2003

2002

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.

Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas

Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Tradeoffs in power-efficient issue queue design.

Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Synchronous Interlocked Pipelines.

Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster

Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001

A circuit level implementation of an adaptive issue queue for power-aware microprocessors.

Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000

Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.

David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook

IEEE Micro, 2000

An Adaptive Issue Queue for Reduced Power at High Performance.

Alper Buyuktosunoglu, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi

Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

1998

Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor.

Phillip J. Restle, Keith A. Jenkins, Alina Deutsch, Peter W. Cook

IEEE J. Solid State Circuits, 1998

1984

Constraint Solver for Generalized IC Layout.

Peter W. Cook

IBM J. Res. Dev., 1984