John-David Wellman

Orcid: 0000-0003-0223-7792

According to our database1, John-David Wellman authored at least 19 papers between 1993 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024

2023
SoCurity: A Design Approach for Enhancing SoC Security.
IEEE Comput. Archit. Lett., 2023

2022
HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs.
CoRR, 2022

A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles.
IEEE Comput. Archit. Lett., 2021

NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021


2020
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.
CoRR, 2020

2017

2008
Phaser: Phased methodology for modeling the system-level effects of soft errors.
IBM J. Res. Dev., 2008

2003
Reducing instruction fetch energy with backwards branch control information and buffering.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2000
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro, 2000

Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

1999
Environment for PowerPC microarchitecture exploration.
IEEE Micro, 1999

1996
Processor modeling and evaluation techniques for early design stage performance comparison.
PhD thesis, 1996

1995
The resource conflict methodology for early-stage design space exploration of superscalar RISC processors.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1993
MIPS-Driven Early Design and Analysis of VLSI CPU Chips.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Evaluating the Communication Performance of MPPs Using Synthetic Sparse Matrix Multiplication Workloads.
Proceedings of the 7th international conference on Supercomputing, 1993


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