Matheus F. Pontes

Orcid: 0000-0003-3749-5193

According to our database1, Matheus F. Pontes authored at least 5 papers between 2018 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Fault Tolerance Evaluation of Different Majority Voter Designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

2018
Reliability evaluation of circuits designed in multi- and single-stage versions.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018


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