René Cumplido
Orcid: 0000-0002-9852-8422Affiliations:
- National Institute of Astrophysics, Optics and Electronics, Puebla, Mexico
According to our database1,
René Cumplido
authored at least 105 papers
between 2001 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2025
Adaptive Intrusion Detection System: Hybrid K-Means and Random Forest Approach with Concept Drift Detection.
Computación y Sistemas (CyS), 2025
2024
Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+.
ACM Trans. Reconfigurable Technol. Syst., December, 2024
A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms.
Microprocess. Microsystems, 2024
2023
Expert Syst. Appl., December, 2023
A secure DWT-based dual watermarking scheme for image authentication and copyright protection.
Multim. Tools Appl., November, 2023
Expert Syst. Appl., November, 2023
2022
Inf. Sci., 2022
ACM Comput. Surv., 2022
Reversible Image Authentication Scheme with Tampering Reconstruction Based on Very Deep Super Resolution Network.
Proceedings of the Advances in Computational Intelligence, 2022
2021
A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks.
J. Sensors, 2021
Eng. Appl. Artif. Intell., 2021
2020
Expert Syst. Appl., 2020
2019
Pattern Recognit. Lett., 2019
J. Parallel Distributed Comput., 2019
J. Parallel Distributed Comput., 2019
Temporal Copy-Move Forgery Detection and Localization Using Block Correlation Matrix.
J. Intell. Fuzzy Syst., 2019
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019
2018
On the design of hardware-software architectures for frequent itemsets mining on data streams.
J. Intell. Inf. Syst., 2018
IACR Cryptol. ePrint Arch., 2018
2017
Mach. Vis. Appl., 2017
A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Approximate frequent itemsets mining on data streams using hashing and lexicographie order in hardware.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
2016
A scalable and customizable processor array for implementing cellular genetic algorithms.
Neurocomputing, 2016
Comput. Electr. Eng., 2016
Comput. Electr. Eng., 2016
An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016
Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016
2015
Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs.
Microprocess. Microsystems, 2015
Microprocess. Microsystems, 2015
Expert Syst. Appl., 2015
An analysis of computational models for accelerating the subtractive pixel adjacency model computation.
Comput. Electr. Eng., 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the New Frontiers in Mining Complex Patterns - 4th International Workshop, 2015
Proceedings of the Genetic and Evolutionary Computation Conference, 2015
2014
Res. Comput. Sci., 2014
Microprocess. Microsystems, 2014
IEICE Electron. Express, 2014
Comput. Electr. Eng., 2014
Comput. Electr. Eng., 2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, 2014
2013
Introduction to the special section on 19th reconfigurable architectures workshop (RAW 2012).
ACM Trans. Reconfigurable Technol. Syst., 2013
Multi-character cost-effective and high throughput architecture for content scanning.
Microprocess. Microsystems, 2013
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256.
Microprocess. Microsystems, 2013
Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011).
Int. J. Reconfigurable Comput., 2013
Expert Syst. Appl., 2013
Area/performance trade-off analysis of an FPGA digit-serial <i>GF</i>(2<sup><i>m</i></sup>)GF(2m) Montgomery multiplier based on LFSR.
Comput. Electr. Eng., 2013
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the Image and Video Technology - 6th Pacific-Rim Symposium, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Proceedings of the Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, 2013
2012
IEICE Electron. Express, 2012
Expert Syst. Appl., 2012
Digit. Signal Process., 2012
Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
2011
J. Signal Process. Syst., 2011
Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware - Experiences on teaching and research.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation.
J. Circuits Syst. Comput., 2010
Hardware architecture for adaptive filtering based on energy-CFAR processor for radar target detection.
IEICE Electron. Express, 2010
IEICE Electron. Express, 2010
A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter.
Digit. Signal Process., 2010
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard.
Comput. Electr. Eng., 2010
Proceedings of the Advances in Pattern Recognition, 2010
On the Design of a Hardware-Software Architecture for Acceleration of SVM's Training Phase.
Proceedings of the Advances in Pattern Recognition, 2010
Proceedings of the Modelling Foundations and Applications - 6th European Conference, 2010
Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010
2009
A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation.
Int. J. Reconfigurable Comput., 2009
IEICE Electron. Express, 2009
An area/performance trade-off analysis of a GF(2<sup>m</sup>) multiplier architecture for elliptic curve cryptography.
Comput. Electr. Eng., 2009
FPGA-architecture for Knowledge-Based Target Detection in Radar Signal Processing.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
Proceedings of the 2009 Mexican International Conference on Computer Science, 2009
Proceedings of the 2009 Mexican International Conference on Computer Science, 2009
2008
Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description.
IEICE Trans. Inf. Syst., 2008
On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm.
Comput. Electr. Eng., 2008
A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter.
Proceedings of the FPL 2008, 2008
Proceedings of the 18th International Conference on Electronics, 2008
2007
Proceedings of the Intelligent Data Engineering and Automated Learning, 2007
2006
Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms.
Computación y Sistemas, 2006
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006
Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture.
Proceedings of the Computational Science and Its Applications, 2006
On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification.
Proceedings of the Progress in Pattern Recognition, 2006
2005
IEEE Trans. Control. Syst. Technol., 2005
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005
Proceedings of the Sixth Mexican International Conference on Computer Science (ENC 2005), 2005
Proceedings of the 42nd Design Automation Conference, 2005
2004
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the 5th Mexican International Conference on Computer Science (ENC 2004), 2004
2001