Samuel Riedel

According to our database, Samuel Riedel authored at least 24 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-Up Cluster Design With High Bandwidth Main Memory Link.

Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Diyou Shen, Bowen Wang, Alessandro Vanelli-Coralli, Luca Benini

IEEE Trans. Computers, November, 2025

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN.

Yichao Zhang, Marco Bertuletti, Sergio Mazzola, Samuel Riedel, Luca Benini

CoRR, September, 2025

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency.

Matteo Perotti, Samuel Riedel, Matheus A. Cavalcante, Luca Benini

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2025

Area Comparison of CHERIoT and PMP in Ibex.

Samuel Riedel, Marno van der Maas, John Thomson, Andreas Kurth, Pirmin Vogel

CoRR, May, 2025

Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC.

Sudipta Das, Samuel Riedel, Mohamed Naeim, Moritz Brunion, Marco Bertuletti, Luca Benini, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic

IEEE Trans. Very Large Scale Integr. Syst., February, 2025

Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication.

Samuel Riedel, Yichao Zhang, Marco Bertuletti, Luca Benini

Proceedings of the 10th International Workshop on Advances in Sensors and Interfaces, 2025

Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks.

Marco Bertuletti, Yichao Zhang, Mahdi Abdollahpour, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters.

Sergio Mazzola, Samuel Riedel, Luca Benini

IEEE Trans. Very Large Scale Integr. Syst., September, 2024

Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs.

Nesara Eranna Bethur, Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

A High-Performance, Energy-Efficient Modular DMA Engine Architecture.

Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini

IEEE Trans. Computers, January, 2024

A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR.

Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini

CoRR, 2024

3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs.

Sudipta Das, Samuel Riedel, Marco Bertuletti, Luca Benini, Moritz Brunion, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios.

Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems Through Polling-Free and Retry-Free Operation.

Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory.

Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini

IEEE Trans. Computers, December, 2023

Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster.

Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS.

Samuel Riedel, Matheus A. Cavalcante, Manos Frouzakis, Domenic Wüthrich, Enis Mustafa, Arlind Billa, Luca Benini

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster.

Samuel Riedel, Gua Hao Khov, Sergio Mazzola, Matheus A. Cavalcante, Renzo Andri, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs.

Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters.

Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration.

Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Banshee: A Fast LLVM-Based RISC-V Binary Translator.

Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect.

Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor.

Andreas Kurth, Samuel Riedel, Florian Zaruba, Torsten Hoefler, Luca Benini

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020