Takuya Ariki
  According to our database1,
  Takuya Ariki
  authored at least 5 papers
  between 2012 and 2025.
  
  
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
  2025
A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os.
    
  
    Proceedings of the IEEE International Solid-State Circuits Conference, 2025
    
  
Crossed Bit Line (CBL) Architecture in 3D Flash Memory CMOS Directly Bonded to Array (CBA) Structure.
    
  
    Proceedings of the IEEE International Memory Workshop, 2025
    
  
  2019
A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology.
    
  
    Proceedings of the IEEE International Solid- State Circuits Conference, 2019
    
  
  2017
    Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
    
  
  2012
A 19nm 112.8mm<sup>2</sup> 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface.
    
  
    Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012