Tong Zhang

According to our database1, Tong Zhang authored at least 118 papers between 2001 and 2019.

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Bibliography

2019
An Exploratory Study on Software-Defined Data Center Hard Disk Drives.
TOS, 2019

Reducing Flash Memory Write Traffic by Exploiting a Few MBs of Capacitor-Powered Write Buffer Inside Solid-State Drives (SSDs).
IEEE Trans. Computers, 2019

2018
Realizing Low-Cost Flash Memory Based Video Caching in Content Delivery Systems.
IEEE Trans. Circuits Syst. Video Techn., 2018

2017
Realizing Transparent OS/Apps Compression in Mobile Devices at Zero Latency Overhead.
IEEE Trans. Computers, 2017

Improving 3D DRAM Fault Tolerance Through Weak Cell Aware Error Correction.
IEEE Trans. Computers, 2017

Facilitating Magnetic Recording Technology Scaling for Data Center Hard Disk Drives through Filesystem-Level Transparent Local Erasure Coding.
Proceedings of the 15th USENIX Conference on File and Storage Technologies, 2017

2016
Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device.
IEEE Trans. VLSI Syst., 2016

On the Use of DRAM with Unrepaired Weak Cells in Computing Systems.
Proceedings of the Second International Symposium on Memory Systems, 2016

Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud.
Proceedings of the Second International Symposium on Memory Systems, 2016

Reducing Solid-State Storage Device Write Stress through Opportunistic In-place Delta Compression.
Proceedings of the 14th USENIX Conference on File and Storage Technologies, 2016

2015
Optimizing the Use of STT-RAM in SSDs Through Data-Dependent Error Tolerance.
IEEE Trans. VLSI Syst., 2015

True-Damage-Aware Enumerative Coding for Improving nand Flash Memory Endurance.
IEEE Trans. VLSI Syst., 2015

On the Case of Using Aggregated Page Programming for Future MLC NAND Flash Memory.
CSSP, 2015

Leveraging Progressive Programmability of SLC Flash Pages to Realize Zero-overhead Delta Compression for Metadata Storage.
Proceedings of the 7th USENIX Workshop on Hot Topics in Storage and File Systems, 2015

How Much Can Data Compressibility Help to Improve NAND Flash Memory Lifetime?
Proceedings of the 13th USENIX Conference on File and Storage Technologies, 2015

2014
Using Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance.
IEEE Trans. VLSI Syst., 2014

Overclocking nand Flash Memory I/O Link in LDPC-Based SSDs.
IEEE Trans. on Circuits and Systems, 2014

Realizing Unequal Error Correction for nand Flash Memory at Minimal Read Latency Overhead.
IEEE Trans. on Circuits and Systems, 2014

OFWAR: Reducing SSD Response Time Using On-Demand Fast-Write-and-Rewrite.
IEEE Trans. Computers, 2014

Enhanced Precision Through Multiple Reads for LDPC Decoding in Flash Memories.
IEEE Journal on Selected Areas in Communications, 2014

Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory.
Proceedings of the IEEE 30th Symposium on Mass Storage Systems and Technologies, 2014

Proximate control stream assisted video transcoding for heterogeneous content delivery network.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Over-clocked SSD: Safely running beyond flash memory chip I/O clock specs.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
DSP Systems Using Three-Dimensional Integration Technology.
Proceedings of the Handbook of Signal Processing Systems, 2013

Using Planar Embedded DRAM in Memory Intensive Signal Processing Circuits: Case Studies on LDPC Decoding and Motion Estimation.
Signal Processing Systems, 2013

Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs.
IEEE Trans. VLSI Syst., 2013

Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes.
IEEE Trans. VLSI Syst., 2013

Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes.
ACM Trans. Design Autom. Electr. Syst., 2013

Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead.
IEEE Trans. on Circuits and Systems, 2013

Using Multilevel Phase Change Memory to Build Data Storage: A Time-Aware System Design Perspective.
IEEE Trans. Computers, 2013

Using Quasi-EZ-NAND Flash Memory to Build Large-Capacity Solid-State Drives in Computing Systems.
IEEE Trans. Computers, 2013

Scheduling Algorithms for Handling Updates in Shingled Magnetic Recording.
Proceedings of the IEEE Eighth International Conference on Networking, 2013

LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives.
Proceedings of the 11th USENIX conference on File and Storage Technologies, 2013

VLSI design of fuzzy-decision bit-flipping QC-LDPC decoder.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache.
IEEE Trans. VLSI Syst., 2012

Estimating Information-Theoretical nand Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration.
IEEE Trans. VLSI Syst., 2012

Joint Source-Channel Coding and Channelization for Embedded Video Processing With Flash Memory Storage.
IEEE Trans. Signal Processing, 2012

Reducing DRAM Image Data Access Energy Consumption in Video Processing.
IEEE Trans. Multimedia, 2012

A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme.
J. Solid-State Circuits, 2012

Reducing latency overhead caused by using LDPC codes in NAND flash memory.
EURASIP J. Adv. Sig. Proc., 2012

Reducing data transfer latency of NAND flash memory with soft-decision sensing.
Proceedings of IEEE International Conference on Communications, 2012

Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011
A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multilevel Phase-Change Memory in the Presence of Significant Resistance Drift.
IEEE Trans. VLSI Syst., 2011

Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM).
IEEE Trans. VLSI Syst., 2011

Design Techniques to Facilitate Processor Power Delivery in 3-D Processor-DRAM Integrated Systems.
IEEE Trans. VLSI Syst., 2011

On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory.
IEEE Trans. on Circuits and Systems, 2011

Using Lossless Data Compression in Data Storage Systems: Not for Saving Space.
IEEE Trans. Computers, 2011

Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology.
Microprocessors and Microsystems - Embedded Hardware Design, 2011

Special session on "3D chips: Challenges and opportunities".
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Exploiting Heat-Accelerated Flash Memory Wear-Out Recovery to Enable Self-Healing SSDs.
Proceedings of the 3rd USENIX Workshop on Hot Topics in Storage and File Systems, 2011

Design techniques to improve the device write margin for MRAM-based cache memory.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Exploiting Memory Device Wear-Out Dynamics to Improve NAND Flash Memory System Performance.
Proceedings of the 9th USENIX Conference on File and Storage Technologies, 2011

2010
Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed.
IEEE Trans. VLSI Syst., 2010

Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage.
IEEE Trans. VLSI Syst., 2010

Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding.
IEEE Trans. VLSI Syst., 2010

A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology.
IEEE Trans. on Circuits and Systems, 2010

Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory.
IEEE Trans. on Circuits and Systems, 2010

Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators.
Sig. Proc.: Image Comm., 2010

DiffECC: Improving SSD Read Performance Using Differentiated Error Correction Coding Schemes.
Proceedings of the MASCOTS 2010, 2010

Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Design of low-power variation tolerant signal processing systems with adaptive finite word-length configuration.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM).
Proceedings of the Design, Automation and Test in Europe, 2010

DSP Systems using Three-Dimensional (3D) Integration Technology.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations.
IEEE Trans. VLSI Syst., 2009

Leveraging Access Locality for the Efficient Use of Multibit Error-Correcting Codes in L2 Cache.
IEEE Trans. Computers, 2009

3-D Data Storage, Power Delivery, and RF/Optical Transceiver - Case Studies of 3-D Integration From System Design Perspectives.
Proceedings of the IEEE, 2009

3D DRAM Design and Application to 3D Multicore Systems.
IEEE Design & Test of Computers, 2009

Using carbon nanotube in digital memories.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Exploratory study on circuit and architecture design of very high density diode-switch phase change memories.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Architecture design exploration of three-dimensional (3D) integrated DRAM.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Data manipulation techniques to reduce phase change memory write energy.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Candidate bit based bit-flipping decoding algorithm for LDPC codes.
Proceedings of the IEEE International Symposium on Information Theory, 2009

Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Improving multi-level NAND flash memory storage reliability using concatenated TCM-BCH coding.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.
Proceedings of the 46th Design Automation Conference, 2009

Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Impacts of though-DRAM vias in 3D processor-DRAM integrated systems.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Impact of parameter accuracy on 3D design.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Bypass Decoding: A Reduced-Complexity Decoding Technique for LDPC-Coded MIMO-OFDM Systems.
IEEE Trans. Vehicular Technology, 2008

Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Energy-efficient soft-output trellis decoder design using trellis quasi-reduction and importance-aware clock skew scheduling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Realization of L2 Cache Defect Tolerance Using Multi-bit ECC.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007
Relaxed K-Best MIMO Signal Detector Design and VLSI Implementation.
IEEE Trans. VLSI Syst., 2007

Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder.
IEEE Trans. on Circuits and Systems, 2007

Design of on-chip error correction systems for multilevel NOR and NAND flash memories.
IET Circuits, Devices & Systems, 2007

Turbo- and LDPC-Coded MIMO-OFDM Systems: A Comparative Study.
Proceedings of the IEEE 18th International Symposium on Personal, 2007

Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Low power soft-output signal detector design for wireless MIMO communication systems.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Low Power Trellis Decoder with Overscaled Supply Voltage.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Triple-rail MOS current mode logic for high-speed self-timed pipeline applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low power state-parallel relaxed adaptive Viterbi decoder design and implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Multilevel flash memory on-chip error correction based on trellis coded modulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Relaxed tree search MIMO signal detection algorithm design and VLSI implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with High Spectral Efficiency.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Parallel high-throughput limited search trellis decoder VLSI design.
IEEE Trans. VLSI Syst., 2005

Block-LDPC: a practical LDPC coding system design approach.
IEEE Trans. on Circuits and Systems, 2005

Self-timed dynamically pipelined adaptive signal processing system: a case study of DLMS equalizer for read channel.
IEEE Trans. on Circuits and Systems, 2005

Parallel Logic Simulation of Million-Gate VLSI Circuits.
Proceedings of the 13th International Symposium on Modeling, 2005

Parallelism/regularity-driven MIMO detection algorithm design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Joint (3, k)-regular LDPC code and decoder/encoder design.
IEEE Trans. Signal Processing, 2004

Joint code-encoder-decoder design for LDPC coding system VLSI implementation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A high throughput limited search trellis decoder for convolutional code decoding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Surface Tortuosity and its Application to Analyzing Cracks in Concrete.
Proceedings of the 17th International Conference on Pattern Recognition, 2004

2003
An FPGA Implementation of (3, 6)-Regular Low-Density Parity-Check Code Decoder.
EURASIP J. Adv. Sig. Proc., 2003

2002
On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001
Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials.
IEEE Trans. Computers, 2001

Volume and Surface Area Distributions of Cracks in Concrete.
Proceedings of the Visual Form 2001, 4th International Workshop on Visual Form, 2001

On finite precision implementation of low density parity check codes decoder.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A class of efficient-encoding generalized low-density parity-check codes.
Proceedings of the IEEE International Conference on Acoustics, 2001

High-performance, low-complexity decoding of generalized low-density parity-check codes.
Proceedings of the Global Telecommunications Conference, 2001


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