Tong Zhang
Orcid: 0009-0009-8005-0043Affiliations:
- Rensselaer Polytechnic Institute, Troy, NY, USA
- Minnesota University, Department of Electrical & Computational Engineering, Minneapolis, MN, USA (PhD 2002)
According to our database1,
Tong Zhang
authored at least 140 papers
between 2001 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Eliminating Storage Management Overhead of Deduplication over SSD Arrays Through a Hardware/Software Co-Design.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
2023
Proceedings of the 16th ACM International Conference on Systems and Storage, 2023
2022
Closing the B+-tree vs. LSM-tree Write Amplification Gap on Modern Storage Hardware with Built-in Transparent Compression.
Proceedings of the 20th USENIX Conference on File and Storage Technologies, 2022
2021
Improving Relational Database Upon the Arrival of Storage Hardware with Built-in Transparent Compression.
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021
Implementing Flash-Cached Storage Systems Using Computational Storage Drive with Built-in Transparent Compression.
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021
KallaxDB: A Table-less Hash-based Key-Value Store on Storage Hardware with Built-in Transparent Compression.
Proceedings of the 17th International Workshop on Data Management on New Hardware, 2021
2020
Architecting Heterogeneous Memory Systems with DRAM Technology Only: A Case Study on Relational Database.
Proceedings of the IEEE/ACM Workshop on Memory Centric High Performance Computing, 2020
WAL-assisted Tiering: Painlessly Improving Your Favorite Log-Structured KV Store Instead of Building a New One.
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020
Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020
Re-think Data Management Software Design Upon the Arrival of Storage Hardware with Built-in Transparent Compression.
Proceedings of the 12th USENIX Workshop on Hot Topics in Storage and File Systems, 2020
POLARDB Meets Computational Storage: Efficiently Support Analytical Workloads in Cloud-Native Relational Database.
Proceedings of the 18th USENIX Conference on File and Storage Technologies, 2020
2019
ACM Trans. Storage, 2019
Reducing Flash Memory Write Traffic by Exploiting a Few MBs of Capacitor-Powered Write Buffer Inside Solid-State Drives (SSDs).
IEEE Trans. Computers, 2019
Mitigate HDD Fail-Slow by Pro-actively Utilizing System-level Data Redundancy with Enhanced HDD Controllability and Observability.
Proceedings of the 35th Symposium on Mass Storage Systems and Technologies, 2019
Simultaneously reducing cost and improving performance of NVM-based block devices via transparent data compression.
Proceedings of the International Symposium on Memory Systems, 2019
2018
CrowdDBS: A Crowdsourced Brightness Scaling Optimization for Display Energy Reduction in Mobile Video.
IEEE Trans. Mob. Comput., 2018
IEEE Trans. Circuits Syst. Video Technol., 2018
2017
Realizing Transparent OS/Apps Compression in Mobile Devices at Zero Latency Overhead.
IEEE Trans. Computers, 2017
IEEE Trans. Computers, 2017
Software Support Inside and Outside Solid-State Devices for High Performance and High Efficiency.
Proc. IEEE, 2017
Facilitating Magnetic Recording Technology Scaling for Data Center Hard Disk Drives through Filesystem-Level Transparent Local Erasure Coding.
Proceedings of the 15th USENIX Conference on File and Storage Technologies, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Guest Editorial Channel Modeling, Coding and Signal Processing for Novel Physical Memory Devices and Systems.
IEEE J. Sel. Areas Commun., 2016
Proceedings of the Second International Symposium on Memory Systems, 2016
Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud.
Proceedings of the Second International Symposium on Memory Systems, 2016
Reducing Solid-State Storage Device Write Stress through Opportunistic In-place Delta Compression.
Proceedings of the 14th USENIX Conference on File and Storage Technologies, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Circuits Syst. Signal Process., 2015
Exploring QoE for Power Efficiency: A Field Study on Mobile Videos with LCD Displays.
Proceedings of the 23rd Annual ACM Conference on Multimedia Conference, MM '15, Brisbane, Australia, October 26, 2015
Leveraging Progressive Programmability of SLC Flash Pages to Realize Zero-overhead Delta Compression for Metadata Storage.
Proceedings of the 7th USENIX Workshop on Hot Topics in Storage and File Systems, 2015
Proceedings of the 13th USENIX Conference on File and Storage Technologies, 2015
2014
J. Signal Process. Syst., 2014
Using Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Realizing Unequal Error Correction for nand Flash Memory at Minimal Read Latency Overhead.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Computers, 2014
IEEE J. Sel. Areas Commun., 2014
Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory.
Proceedings of the IEEE 30th Symposium on Mass Storage Systems and Technologies, 2014
Proximate control stream assisted video transcoding for heterogeneous content delivery network.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
2013
Proceedings of the Handbook of Signal Processing Systems, 2013
Using Planar Embedded DRAM in Memory Intensive Signal Processing Circuits: Case Studies on LDPC Decoding and Motion Estimation.
J. Signal Process. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes.
ACM Trans. Design Autom. Electr. Syst., 2013
Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Using Multilevel Phase Change Memory to Build Data Storage: A Time-Aware System Design Perspective.
IEEE Trans. Computers, 2013
Using Quasi-EZ-NAND Flash Memory to Build Large-Capacity Solid-State Drives in Computing Systems.
IEEE Trans. Computers, 2013
Proceedings of the IEEE Eighth International Conference on Networking, 2013
LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives.
Proceedings of the 11th USENIX conference on File and Storage Technologies, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Estimating Information-Theoretical nand Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Joint Source-Channel Coding and Channelization for Embedded Video Processing With Flash Memory Storage.
IEEE Trans. Signal Process., 2012
IEEE Trans. Multim., 2012
A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme.
IEEE J. Solid State Circuits, 2012
EURASIP J. Adv. Signal Process., 2012
Mutual-Information Optimized Quantization for LDPC Decoding of Accurately Modeled Flash Data
CoRR, 2012
Proceedings of IEEE International Conference on Communications, 2012
Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
2011
A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multilevel Phase-Change Memory in the Presence of Significant Resistance Drift.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Design Techniques to Facilitate Processor Power Delivery in 3-D Processor-DRAM Integrated Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE Trans. Computers, 2011
Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology.
Microprocess. Microsystems, 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Exploiting Heat-Accelerated Flash Memory Wear-Out Recovery to Enable Self-Healing SSDs.
Proceedings of the 3rd USENIX Workshop on Hot Topics in Storage and File Systems, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Exploiting Memory Device Wear-Out Dynamics to Improve NAND Flash Memory System Performance.
Proceedings of the 9th USENIX Conference on File and Storage Technologies, 2011
2010
Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators.
Signal Process. Image Commun., 2010
DiffECC: Improving SSD Read Performance Using Differentiated Error Correction Coding Schemes.
Proceedings of the MASCOTS 2010, 2010
Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Design of low-power variation tolerant signal processing systems with adaptive finite word-length configuration.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM).
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Leveraging Access Locality for the Efficient Use of Multibit Error-Correcting Codes in L2 Cache.
IEEE Trans. Computers, 2009
3-D Data Storage, Power Delivery, and RF/Optical Transceiver - Case Studies of 3-D Integration From System Design Perspectives.
Proc. IEEE, 2009
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Exploratory study on circuit and architecture design of very high density diode-switch phase change memories.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the IEEE International Symposium on Information Theory, 2009
Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Improving multi-level NAND flash memory storage reliability using concatenated TCM-BCH coding.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009
Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2008
Bypass Decoding: A Reduced-Complexity Decoding Technique for LDPC-Coded MIMO-OFDM Systems.
IEEE Trans. Veh. Technol., 2008
Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Energy-efficient soft-output trellis decoder design using trellis quasi-reduction and importance-aware clock skew scheduling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Design of on-chip error correction systems for multilevel NOR and NAND flash memories.
IET Circuits Devices Syst., 2007
Proceedings of the IEEE 18th International Symposium on Personal, 2007
Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Low power soft-output signal detector design for wireless MIMO communication systems.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits.
Proceedings of the 25th International Conference on Computer Design, 2007
2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with High Spectral Efficiency.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Self-timed dynamically pipelined adaptive signal processing system: a case study of DLMS equalizer for read channel.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Proceedings of the 13th International Symposium on Modeling, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
IEEE Trans. Signal Process., 2004
Joint code-encoder-decoder design for LDPC coding system VLSI implementation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A high throughput limited search trellis decoder for convolutional code decoding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 17th International Conference on Pattern Recognition, 2004
2003
EURASIP J. Adv. Signal Process., 2003
2002
On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
2001
Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials.
IEEE Trans. Computers, 2001
Proceedings of the Visual Form 2001, 4th International Workshop on Visual Form, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
High-performance, low-complexity decoding of generalized low-density parity-check codes.
Proceedings of the Global Telecommunications Conference, 2001