Toru Nakura
Orcid: 0000-0001-5945-3918
According to our database1,
Toru Nakura
authored at least 94 papers
between 2000 and 2025.
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Bibliography
2025
IEICE Trans. Electron., 2025
A 10ps-Order Flexible Resolution Time-to-Digital Converter with Linearity Calibration and Legacy FPGA.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
2024
Measurement of SET pulse width modulation in CMOS combinational logic by laser-induced fault injection.
IEICE Electron. Express, 2024
2023
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023
Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop.
IEICE Trans. Electron., October, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
2019
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field.
IEEE Trans. Instrum. Meas., 2019
A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool.
IEICE Electron. Express, 2019
Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes.
IEICE Electron. Express, 2019
2018
IEICE Trans. Electron., 2018
IEICE Trans. Electron., 2018
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
IEICE Electron. Express, 2018
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment.
J. Electron. Test., 2018
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
2017
IEICE Trans. Electron., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Impulse signal generator based on current-mode excitation and transmission line resonator.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017
A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Extension of power supply impedance emulation method on ATE for multiple power domain.
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the Computational Imaging XV, Burlingame, 2017
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors.
J. Circuits Syst. Comput., 2016
An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface.
IEICE Trans. Electron., 2016
Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing.
IEICE Trans. Electron., 2016
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing.
J. Electron. Test., 2016
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board.
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 11th European Workshop on Microelectronics Education, 2016
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
IEICE Trans. Electron., 2015
Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline.
IEICE Electron. Express, 2015
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator.
Proceedings of the Nordic Circuits and Systems Conference, 2015
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills.
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
2013
IEICE Trans. Electron., 2013
Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter.
IEICE Trans. Electron., 2012
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme.
IEICE Trans. Electron., 2012
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction.
IEICE Trans. Electron., 2012
Power integrity control of ATE for emulating power supply fluctuations on customer environment.
Proceedings of the 2012 IEEE International Test Conference, 2012
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
IEICE Trans. Electron., 2011
1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells.
IEICE Trans. Electron., 2011
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch.
IEICE Trans. Electron., 2011
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter.
IEICE Trans. Electron., 2011
Proceedings of the International SoC Design Conference, 2011
On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IEICE Trans. Electron., 2010
A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Electron. Express, 2010
Time-to-digital converter based on time difference amplifier with non-linearity calibration.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability.
IEICE Trans. Electron., 2009
Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
2005
IEICE Trans. Electron., 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2000
IEEE J. Solid State Circuits, 2000