Yun Wang
Orcid: 0000-0001-7773-1619Affiliations:
- Fudan University, State Key Laboratory of Integrated Chips and Systems, Shanghai, China
- Tokyo Institute of Technology, Department of Electrical and Electronic Engineering, Japan (PhD 2019)
According to our database1,
Yun Wang
authored at least 45 papers
between 2016 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
A 2.4-GHz-BW 59.7-dB-Range 0.39-dB-Error dB-Linear VGA Featuring -40 °C~110 °C and ±10%-Supply PVT Robustness in 40-Nm CMOS.
IEEE J. Solid State Circuits, September, 2025
A 1-21-GHz, 1.95-3.1-dB NF Ultra-Wideband LNA With Gₘ-Assisted-Feedback Noise Suppression Achieving 140-Gb/s Data Rate in 40-nm CMOS.
IEEE J. Solid State Circuits, September, 2025
IEICE Electron. Express, 2025
2024
Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference Canceller.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024
A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression.
IEEE J. Solid State Circuits, April, 2024
A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation.
IEEE J. Solid State Circuits, February, 2024
A 140-Gbps 1-to-21-GHz Ultra-Wideband LNA Achieving 1.95-to-3-dB NF Using Gm-Assisted-Feedback Noise Suppression Technique in 40nm Bulk CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the IEEE International Conference on Integrated Circuits, 2024
2023
A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations.
IEEE J. Solid State Circuits, December, 2023
A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station.
IEEE J. Solid State Circuits, 2023
A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A 115-325MHz Wideband Analog Baseband with 0.5dB-Step Variable Gain Amplifier and Six-order Reconfigurable Gm-C Lowpass Filter.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
A Compact 144% Fractional Bandwidth CMOS Power Amplifier With an Optimization of Synthesized High-Order Matching Network.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
A 4.7-to-18-GHz Ultra-Wideband Variable-Gain Balun-LNA Using 3<sup>rd</sup>-Order-Band-Pass Input Matching in 40-nm CMOS.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
An 8.5-dB Insertion Loss and 0.8° RMS Phase Error Ka-Band CMOS Hybrid Phase Shifter Featuring Nonuniform Matching for Satellite Communication.
IEICE Trans. Electron., October, 2022
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal.
IEEE J. Solid State Circuits, 2022
A 39-GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-Station.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth.
IEEE J. Solid State Circuits, 2021
A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems.
IEEE J. Solid State Circuits, 2021
A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR.
IEEE J. Solid State Circuits, 2020
A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019
A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio.
IEEE J. Solid State Circuits, 2019
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance.
IEEE J. Solid State Circuits, 2019
A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019
0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS.
IEICE Trans. Electron., 2018
2017
IEEE J. Solid State Circuits, 2017
A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256 QAM Wireless Transmission in 65-nm CMOS.
IEICE Trans. Electron., 2017
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016