Chunyu Peng

According to our database, Chunyu Peng authored at least 81 papers between 2015 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A 28 nm Dual-Mode SRAM-CIM Macro With Local Computing Cell for CNNs and Grayscale Edge Detection.

Chunyu Peng, Xiaohang Chen, Mengya Gao, Jiating Guo, Lijun Guan, Chenghu Dai, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., August, 2025

Full-Array Boolean Logic CIM Macro With Self-Recycling 10T-SRAM Cell for AES Systems.

Xin Li, Ying Pan, Qian Jin, Lintao Chen, Yang Lou, Baofa Wu, Jiajun Long, Yongliang Zhou, Chunyu Peng, Xiulong Wu, Zhiting Lin

IEEE Trans. Very Large Scale Integr. Syst., August, 2025

A 28-nm Cascode Current Mirror-Based Inconsistency-Free Charging-and-Discharging SRAM-CIM Macro for High-Efficient Convolutional Neural Networks.

Chunyu Peng, Jiating Guo, Shengyuan Yan, Yiming Wei, Xiaohang Chen, Wenjuan Lu, Chenghu Dai, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., July, 2025

A 28-nm 9T1C SRAM-Based CIM Macro With Hierarchical Capacitance Weighting and Two-Step Capacitive Comparison ADCs for CNNs.

Zhiting Lin, Runru Yu, Yunhao Li, Miao Long, Yu Liu, Jianxing Zhou, Da Huo, Qingchuan Zhu, Yue Zhao, Lintao Chen, Chunyu Peng, Qiang Zhao, Xin Li, Chenghu Dai, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., July, 2025

8T-SRAM Computing-in-Memory Macro with Bitline Leakage Compensation.

Chunyu Peng, Junbo Chen, Mengyi Zhao, Wenjuan Lu, Zhiting Lin, Licai Hao, Xin Li, Chenghu Dai, Xiulong Wu

Circuits Syst. Signal Process., July, 2025

A High-Performance and High-Robustness Triple-Node-Upset Tolerant Latch Based on Redundant-Node Hardening.

Qiang Zhao, Qingyi Liu, Xinyi Zhang, Licai Hao, Xin Li, Shengyue Zhang, Chunyu Peng, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., May, 2025

High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200-237.5 TOPS/W.

Wenjuan Lu, Lubin Xiang, Ling Wang, Chunyu Peng, Chenghu Dai, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., April, 2025

A Low-Cost and Triple-Node-Upset Self-Recoverable Latch Design With Low Soft Error Rate.

Licai Hao, Lang Tian, Hao Wang, Shiyu Zhao, Qiang Zhao, Chunyu Peng, Chenghu Dai, Zhi-Ting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., April, 2025

High-throughput in-memory bitwise computing based on a coupled dual-SRAM array with independent operands.

Hongbiao Wu, Zhiting Lin, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng

Int. J. Circuit Theory Appl., April, 2025

Real-time bit-line leakage balance circuit with four-input low-offset SA considering threshold voltage for SRAM stability design.

Chunyu Peng, Wei Hu, Hao Zheng, Wenjuan Lu, Chenghu Dai, Xiulong Wu, Zhiting Lin, Junning Chen

Int. J. Circuit Theory Appl., April, 2025

A double-modules interlocking triple-node upset-tolerant latch design.

Shiyu Zhao, Qiang Zhao, Licai Hao, Hao Wang, Lang Tian, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu

Microelectron. J., 2025

A low-power, area-efficient digital decimation filter with column-shared counter topology for CMOS image sensor.

Qiang Zhao, Jianmin Zhang, Shiqi Dang, Bin Qiang, Xiuying Wang, Xin Li, Zhigang Li, Chunyu Peng, Zhiting Lin, Xiulong Wu

Microelectron. J., 2025

A residual pulse broadening interpolation quantization column-level ADC architecture for CMOS image sensors.

Qiang Zhao, Ziming Wang, Chunhui Fan, Bin Qiang, Jitao Xu, Xin Li, Zhigang Li, Licai Hao, Chunyu Peng, Zhiting Lin, Xiulong Wu

Microelectron. J., 2025

An interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors.

Qiang Zhao, Shiqi Dang, Zhendong Niu, Bin Qiang, Chunhui Fan, Zhigang Li, Licai Hao, Chunyu Peng, Zhiting Lin, Xiulong Wu

Microelectron. J., 2025

Hybrid MOSFET-TFET 11T SRAM cell with high write speed and free half-selected disturbance.

Wenjuan Lu, Chuang Wang, Wei Hu, Chenghu Dai, Chunyu Peng, Zhiting Lin, Xiulong Wu

Microelectron. J., 2025

A high charge-discharge stability SRAM 10T1C XOR CIM macro applied in BCAM and Hamming distance.

Li Liu, Wei Hu, Zhen Yang, Yiming Wei, Chunyu Peng, Xiulong Wu, Zhiting Lin, Wenjuan Lu, Yongliang Zhou, Junning Chen

Microelectron. J., 2025

Low-power 12T TFET-MOSFET hybrid SRAM bitcell and hybrid 8T SRAM array based on multiplexing strategy.

Wei Hu, Qizhong Zhang, Chenghu Dai, Chunyu Peng, Wenjuan Lu, Xiulong Wu

Microelectron. J., 2025

A PVT-insensitive 7T SRAM CIM macro for multibit multiplication with dynamic matching quantization circuits.

Chenghu Dai, Jianhao Zhang, Ruixuan Wang, Junbo Chen, Wei Hu, Licai Hao, Wenjuan Lu, Zhiting Lin, Chunyu Peng, Xiulong Wu

Microelectron. J., 2025

MTJ based Temperature-Adaptive VCO (TAVCO) for Compensating CP-PLL Frequency Drift.

Yongliang Zhou, Jingxue Zhong, Yingxue Sun, Chengxing Dai, Weizhe Tan, Chunyu Peng, Wenjuan Lu, Xin Li, Zhiting Lin, Xiulong Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

MTJ based temperature compensated beta multiplier Voltage Reference.

Yongliang Zhou, Yingxue Sun, Jingxue Zhong, Chengxing Dai, Weizhe Tan, Chunyu Peng, Xin Li, Zhigang Li, Zhiting Lin, Xiulong Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

High-Performance Latch Designs of Double-Node-Upset Self-Recovery and Triple-Node-Upset Tolerance for Aerospace Applications.

Chunyu Peng, Lang Tian, Licai Hao, Qiang Zhao, Chenghu Dai, Zhiting Lin, Xiulong Wu

IEEE Trans. Aerosp. Electron. Syst., October, 2024

Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense.

Yongliang Zhou, Xiao Lin, Zixuan Zhou, Yingxue Sun, Yiming Wei, Zhen Yang, Chengxing Dai, Jingxue Zhong, Xiulong Wu, Chunyu Peng

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024

Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design.

Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., May, 2024

Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies.

Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., April, 2024

Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory.

Li Liu, Dele Tai, Bin Qiang, Lijun Guan, Chunyu Peng, Chenghu Dai, Licai Hao, Wenjuan Lu, Zhiting Lin, Qiang Zhao, Xiulong Wu

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations.

Chenghu Dai, Zihua Ren, Lijun Guan, Haitao Liu, Mengya Gao, Wenjuan Lu, Zhiyong Pang, Chunyu Peng, Xiulong Wu

Microelectron. J., February, 2024

A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.

Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices.

Yongliang Zhou, Yiming Wei, Tianzhu Xiong, Zixuan Zhou, Zhen Yang, Xiao Lin, Wei Hu, Xiulong Wu, Chunyu Peng

Microelectron. J., 2024

Design of polarity hardening SRAM for mitigating single event multiple node upsets.

Shiyu Zhao, Qiang Zhao, Licai Hao, Chunyu Peng, Yaling Wang, Wenjuan Lu, Zhiting Lin, Xiulong Wu

Microelectron. J., 2024

An 11-bit two-step column-shared ADC based on Flash/SS architecture for CMOS image sensor.

Qiang Zhao, Jitao Xu, Chunhui Fan, Ziming Wang, Ruitong Hu, Xin Li, Zhigang Li, Licai Hao, Chunyu Peng, Zhiting Lin, Xiulong Wu

Microelectron. J., 2024

Configurable in-memory computing architecture based on dual-port SRAM.

Yue Zhao, Yunlong Liu, Jian Zheng, Zhongzhen Tong, Xin Wang, Runru Yu, Xiulong Wu, Yongliang Zhou, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin

Microelectron. J., 2024

High energy efficient and configurable CIM macro for image processing.

Chunyu Peng, Shengyuan Yan, Huayi Ding, Yana Wang, Wenjuan Lu, Chenghu Dai, Xin Li, Wei Hu, Xiulong Wu

Microelectron. J., 2024

Cross-coupled 4T2R multi-logic in-memory computing circuit design.

Zhiting Lin, Changxin Yue, Ke Li, Qiushi Feng, Siyan Li, Yue Zhao, Yuanyang Wang, Jiaqi Chen, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Chenghu Dai, Licai Hao, Xiulong Wu

Microelectron. J., 2024

A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC.

Zhiting Lin, Runru Yu, Da Huo, Qingchuan Zhu, Miao Long, Yongqi Qin, Yanchun Liu, Lintao Chen, Simin Wang, Ting Wang, Yousheng Xing, Zeshi Wen, Yu Liu, Xin Li, Chenghu Dai, Qiang Zhao, Chunyu Peng, Xiulong Wu

Microelectron. J., 2024

Corrigendum to "A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC" [145, March 2024, 106124.

Xin Li, Mengya Gao, Zihua Ren, Kefeng Yu, Wenjuan Lu, Chenghu Dai, Wei Hu, Chunyu Peng, Xiulong Wu

Microelectron. J., 2024

A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC.

Xin Li, Mengya Gao, Zihua Ren, Kefeng Yu, Wenjuan Lu, Chenghu Dai, Wei Hu, Chunyu Peng, Xiulong Wu

Microelectron. J., 2024

A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM.

Yongliang Zhou, Zhen Yang, Yiming Wei, Xiao Lin, Saiai Wu, Wenjuan Lu, Chunyu Peng, Xin Li, Xiulong Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

SRAM-Based Digital CIM Macro for Linear Interpolation and MAC.

Zhiting Lin, Yunlong Liu, Yaling Wang, Yue Zhao, Chunyu Peng, Xiulong Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Novel radiation-hardened-by-design (RHBD) 14T memory cell for aerospace applications in 65 nm CMOS technology.

Pengfei Li, Xiuying Wang, Yin Zhang, Haoyu Wang, Jianjie Lu, Qiang Zhao, Licai Hao, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu

Microelectron. J., November, 2023

A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store.

Zhiting Lin, Shaoying Zhang, Qian Jin, Jianping Xia, Yunwei Liu, Kefeng Yu, Jian Zheng, Xiaoming Xu, Xing Fan, Ke Li, Zhongzhen Tong, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao

IEEE Trans. Very Large Scale Integr. Syst., June, 2023

In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations.

Zhiting Lin, Zhongzhen Tong, Fangming Wang, Jin Zhang, Yue Zhao, Peng Sun, Tian Xu, Cheng Zhang, Xingwei Li, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Junning Chen

IEEE J. Solid State Circuits, May, 2023

High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications.

Zhiting Lin, Min Chen, Peng Sun, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Threshold Switching Memristor-Based Voltage Regulative Circuit.

Zuheng Wu, Changwei Zhang, Jianxun Zou, Chunyu Peng, Xiulong Wu

IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Design of radiation-hardened memory cell by polar design for space applications.

Licai Hao, Li Liu, Qi Shi, Bin Qiang, Zhengya Li, Nianlong Liu, Chenghu Dai, Qiang Zhao, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu

Microelectron. J., February, 2023

Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design.

Chenghu Dai, Yuanyuan Du, Qi Shi, Ruixuan Wang, Hao Zheng, Wenjuan Lu, Chunyu Peng, Licai Hao, Zhiting Lin, Xiulong Wu

Microelectron. J., February, 2023

Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments.

Qiang Zhao, Hanwen Dong, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Junning Chen, Xiulong Wu

Int. J. Circuit Theory Appl., January, 2023

Radiation-hardened 14T SRAM cell by polar design for space applications.

Licai Hao, Bin Qiang, Chenghu Dai, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Li Liu, Qiang Zhao, Xiulong Wu, Fei Sun

IEICE Electron. Express, 2023

MS3DAAM: Multi-scale 3-D Analytic Attention Module for Convolutional Neural Networks.

Yincong Wang, Shoubiao Tan, Chunyu Peng

Proceedings of the Neural Information Processing - 30th International Conference, 2023

First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology.

Kaifeng Wang, Yongqin Wu, Ye Ren, Renjie Wei, Zerui Chen, Jianfeng Hang, Zhixuan Wang, Fangxing Zhang, Lining Zhang, Chunyu Peng, Xiulong Wu, Le Ye, Kai Zheng, Jin Kang, Xusheng Wu, Weihai Bu, Ru Huang, Qianqian Huang

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing.

Yue Zhao, Zhiting Lin, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Zhongzhen Tong, Junning Chen

IEEE Trans. Very Large Scale Integr. Syst., 2022

In-Memory Multibit Multiplication Based on Bitline Shifting.

Jin Zhang, Zhiting Lin, Xiulong Wu, Zhongzhen Tong, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Hongbiao Wu, Junning Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point.

Pei Huang, Kuan-Chang Chang, Junlin Ge, Chunyu Peng, Xiulong Wu, Junning Chen, Zhiting Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2022

An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset.

Yue Zhao, Jinkai Wang, Zhongzhen Tong, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin

Microelectron. J., 2022

Novel radiation-hardened latch design for space-radiation environments.

Qiang Zhao, Hanwen Dong, Licai Hao, Xiuying Wang, Chunyu Peng, Xiulong Wu

IEICE Electron. Express, 2022

2021

Reverse Bias Current Eliminated, Read-Separated, and Write-Enhanced Tunnel FET SRAM.

Chunyu Peng, Zhou Yang, Zhiting Lin, Xiulong Wu, Xuan Li

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption.

Zhiting Lin, Luanyun Li, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports.

Zhiting Lin, Zhiyong Zhu, Honglan Zhan, Chunyu Peng, Xiulong Wu, Yuan Yao, Jianchao Niu, Junning Chen

IEEE J. Solid State Circuits, 2021

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing.

Zhiting Lin, Honglan Zhan, Zhongwei Chen, Chunyu Peng, Xiulong Wu, Wenjuan Lu, Qiang Zhao, Xuan Li, Junning Chen

IEEE J. Solid State Circuits, 2021

2020

Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications.

Qiang Zhao, Chunyu Peng, Junning Chen, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., 2020

In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands.

Zhiting Lin, Honglan Zhan, Xuan Li, Chunyu Peng, Wenjuan Lu, Xiulong Wu, Junning Chen

IEEE Trans. Very Large Scale Integr. Syst., 2020

Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield.

Zhiting Lin, Yong Wang, Chunyu Peng, Xiulong Wu, Xuan Li, Junning Chen

IEEE Trans. Very Large Scale Integr. Syst., 2020

Challenges and Solutions of the TFET Circuit Design.

Zhiting Lin, Panpan Chen, Le Ye, Xu Yan, Lanzhi Dong, Shuguang Zhang, Zhou Yang, Chunyu Peng, Xiulong Wu, Junning Chen

IEEE Trans. Circuits Syst., 2020

A new reading mode based on balanced pre-charging and group decoding.

Wenjuan Lu, Guoying Qin, Zhiting Lin, Xiulong Wu, Chunyu Peng

IEICE Electron. Express, 2020

2019

Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.

Chunyu Peng, Jiati Huang, Changyong Liu, Qiang Zhao, Songsong Xiao, Xiulong Wu, Zhiting Lin, Junning Chen, Xuan Zeng

IEEE Trans. Very Large Scale Integr. Syst., 2019

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS.

Qiang Zhao, Chunyu Peng, Changyong Liu, Xiulong Wu

IEICE Electron. Express, 2019

An inverter chain with parallel output nodes for eliminating single-event transient pulse.

Changyong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2019

A single event upset tolerant latch with parallel nodes.

Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2019

A high performance radiation-hardened SRAM cell based on Quatro.

Yuyong Jia, Zhengping Li, Chunyu Peng

IEICE Electron. Express, 2019

2018

Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application.

Chunyu Peng, Songsong Xiao, Wenjuan Lu, Jingbo Zhang, Xiulong Wu, Junning Chen, Zhiting Lin

IEEE Trans. Very Large Scale Integr. Syst., 2018

Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique.

Chunyu Peng, Lingyu Kong, Xiulong Wu, Zhiting Lin, Hua Xu, Junning Chen, Xuan Zeng

IEICE Electron. Express, 2018

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.

Changyong Liu, Chunyu Peng, Zhiting Lin, Xiulong Wu, Ziyang Chen, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2018

2017

A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process.

Zhiting Lin, Xiulong Wu, Zhi Li, Lijun Guan, Chunyu Peng, Changyong Liu, Junning Chen

IEEE J. Solid State Circuits, 2017

A radiation harden enhanced Quatro (RHEQ) SRAM cell.

Chunyu Peng, Ziyang Chen, Jingbo Zhang, Songsong Xiao, Changyong Liu, Xiulong Wu, Zhiting Lin

IEICE Electron. Express, 2017

2016

Read/write margin enhanced 10T SRAM for low voltage application.

Chunyu Peng, Lijun Guan, Wenjuan Lu, Xiulong Wu, Xincun Ji

IEICE Electron. Express, 2016

Additive-calibration scheme for leakage compensation of low voltage SRAM.

Chunyu Peng, Xiangwen An, Zhiting Lin, Xiulong Wu, Wei Hong

IEICE Electron. Express, 2016

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier.

Zhengping Li, Chunyu Peng, Wenjuan Lu, Lijun Guan, Youwu Tao, Xincun Ji, Junning Chen

IEICE Electron. Express, 2016

2015

Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier.

Shoubiao Tan, Wenjuan Lu, Chunyu Peng, Zhengping Li, Youwu Tao, Junning Chen

Frontiers Inf. Technol. Electron. Eng., 2015

Image-to-class distance ratio: A feature filtering metric for image classification.

Shoubiao Tan, Li Liu, Chunyu Peng, Ling Shao

Neurocomputing, 2015

Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102].

Chunyu Peng, Youwu Tao, Wenjuan Lu, Zhengping Li, Xinchun Ji, Jinlong Yan, Junning Chen

IEICE Electron. Express, 2015

A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier.

Chunyu Peng, Youwu Tao, Wenjuan Lu, Zhengping Li, Xinchun Ji, Jinlong Yan, Junning Chen

IEICE Electron. Express, 2015

Human dynamics in mobile social networks: A study of inter-node relationships.

Zhiting Lin, Chunyu Peng, Xiulong Wu, Xiufang Jiang

Proceedings of the 12th International Conference on Fuzzy Systems and Knowledge Discovery, 2015