Cong Xu
Affiliations:- University of California Santa Barbara (UCSB), CA, USA
- Hewlett Packard Labs, Palo Alto, CA, USA
- Pennsylvania State University, PA, USA (PhD 2015)
According to our database1,
Cong Xu
authored at least 41 papers
between 2010 and 2022.
Collaborative distances:
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Bibliography
2022
IEEE Trans. Big Data, 2022
2019
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.
IEEE Trans. Parallel Distributed Syst., 2019
2018
SmoothOut: Smoothing Out Sharp Minima for Generalization in Large-Batch Deep Learning.
CoRR, 2018
Toward Cost-Effective Memory Scaling in Clouds: Symbiosis of Virtual and Physical Memory.
Proceedings of the 11th IEEE International Conference on Cloud Computing, 2018
2017
Proceedings of the Advances in Neural Information Processing Systems 30: Annual Conference on Neural Information Processing Systems 2017, 2017
Proceedings of the IEEE International Conference on Computer Vision, 2017
2016
J. Comput. Sci. Technol., 2016
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
ACM Trans. Design Autom. Electr. Syst., 2015
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.
IEEE Trans. Multi Scale Comput. Syst., 2015
IPSJ Trans. Syst. LSI Des. Methodol., 2015
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the 47th Design Automation Conference, 2010