Gerald Strevig
Orcid: 0009-0005-8265-2970
According to our database1,
Gerald Strevig
authored at least 8 papers
between 2013 and 2025.
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Bibliography
2025
2.2 IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
37.1 IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area, and Reliability.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2022
POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2020
IBM z15: Physical design improvements to significantly increase content in the same technology.
IBM J. Res. Dev., 2020
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.
IEEE J. Solid State Circuits, 2014
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013