Javier Diaz-Fortuny
Orcid: 0000-0002-8186-071X
According to our database1,
Javier Diaz-Fortuny
authored at least 20 papers
between 2017 and 2023.
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Bibliography
2023
Using dedicated device arrays for the characterization of TDDB in a scaled HK/MG technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
The Role of Mobility Degradation in the BTI-Induced RO Aging in a 28-nm Bulk CMOS Technology: (Student paper).
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
A Ring-Oscillator-Based Degradation Monitor Concept with Tamper Detection Capability.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2020
Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits.
IEEE Trans. Instrum. Meas., 2020
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level.
Integr., 2020
2019
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI.
IEEE J. Solid State Circuits, 2019
TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level.
Proceedings of the 16th International Conference on Synthesis, 2019
A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models.
Proceedings of the 15th International Conference on Synthesis, 2018
Proceedings of the 15th International Conference on Synthesis, 2018
A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation.
Proceedings of the 15th International Conference on Synthesis, 2018
Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
2017
A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging.
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the 14th International Conference on Synthesis, 2017