Luca Collini

Orcid: 0000-0003-2367-6700

According to our database1, Luca Collini authored at least 21 papers between 2013 and 2025.

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Bibliography

2025
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction.
ACM Trans. Design Autom. Electr. Syst., July, 2025

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction.
CoRR, June, 2025

VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification.
CoRR, May, 2025

MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Models.
CoRR, May, 2025

Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective.
CoRR, March, 2025

The Impact of Logic Locking on Confidentiality: An Automated Evaluation.
Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

Large Language Models (LLMs) for Verification, Testing, and Design.
Proceedings of the IEEE European Test Symposium, 2025

2024
Using Static Analysis for Enhancing HLS Security.
IEEE Embed. Syst. Lett., June, 2024

C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap.
CoRR, 2024

C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?
CoRR, 2024

2023
Optimizing the Use of Behavioral Locking for High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

ConVERTS: Contrastively Learning Structurally InVariant Netlist Representations.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Reconfigurable Logic for Hardware IP Protection: Opportunities and Challenges.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A Composable Design Space Exploration Framework to Optimize Behavioral Locking.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

ALICE: an automatic design flow for eFPGA redaction.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Designing ML-resilient locking at register-transfer level.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
On the Optimization of Behavioral Logic Locking for High-Level Synthesis.
CoRR, 2021

2016
Oscillations of a rocking block with an added pendulum.
J. Syst. Control. Eng., 2016

2013
Modal tests on buildings: correlating large amounts of acquisitions with different space-time collocations.
J. Syst. Control. Eng., 2013


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