Ankur Agrawal
Orcid: 0000-0001-9397-8726
According to our database1,
Ankur Agrawal
authored at least 56 papers
between 2008 and 2024.
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Bibliography
2024
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 7th International Conference on Medical and Health Informatics, 2023
2022
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.
IEEE J. Solid State Circuits, 2022
Benchmarking the Interactions among Green and Sustainable Vendor Selection Attributes.
Adv. Oper. Res., 2022
800 Gbps Fully Integrated Silicon Photonics Transmitter for Data Center Applications.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022
2021
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2021
2020
Quality assurance and enrichment of biological and biomedical ontologies and terminologies.
BMC Medical Informatics Decis. Mak., 2020
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
400Gbps Fully Integrated DR4 Silicon Photonics Transmitter for Data Center Applications.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020
Proceedings of the IEEE Intelligent Vehicles Symposium, 2020
Identifying the Operational Design Domain for an Automated Driving System through Assessed Risk.
Proceedings of the IEEE Intelligent Vehicles Symposium, 2020
2019
Proceedings of the 7th International Conference on Learning Representations, 2019
Proceedings of the 2019 IEEE International Conference on Bioinformatics and Biomedicine, 2019
DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019
2018
Evaluating lexical similarity and modeling discrepancies in the procedure hierarchy of SNOMED CT.
BMC Medical Informatics Decis. Mak., 2018
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the Group Interaction Frontiers in Technology Workshop, 2018
Proceedings of the Extended Abstracts of the 2018 CHI Conference on Human Factors in Computing Systems, 2018
AdaComp : Adaptive Residual Gradient Compression for Data-Parallel Distributed Training.
Proceedings of the Thirty-Second AAAI Conference on Artificial Intelligence, 2018
2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Analysis of the consistency in the structural modeling of SNOMED CT and CORE problem list concepts.
Proceedings of the 2017 IEEE International Conference on Bioinformatics and Biomedicine, 2017
Proceedings of the 2017 IEEE Workshop on Advanced Robotics and its Social Impacts, 2017
Terrain Adaptive Posture Correction in Quadruped for Locomotion On Unstructured Terrain.
Proceedings of the Advances in Robotics, 2017
2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016
Int. J. Data Min. Bioinform., 2016
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
Proceedings of the 2016 ACM Conference on Designing Interactive Systems, DIS '16, Brisbane, QLD, Australia, June 04, 2016
2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015
A tribal abstraction network for SNOMED CT target hierarchies without attribute relationships.
J. Am. Medical Informatics Assoc., 2015
Proceedings of the 32nd International Conference on Machine Learning, 2015
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 33rd Annual ACM Conference Extended Abstracts on Human Factors in Computing Systems, 2015
Algorithmic detection of inconsistent modeling among SNOMED CT concepts by combining lexical and structural indicators.
Proceedings of the 2015 IEEE International Conference on Bioinformatics and Biomedicine, 2015
2014
Contrasting lexical similarity and formal definitions in SNOMED CT: Consistency and implications.
J. Biomed. Informatics, 2014
Proceedings of the 20th International Conference on Management of Data, 2014
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
The readiness of SNOMED problem list concepts for meaningful use of electronic health records.
Artif. Intell. Medicine, 2013
Proceedings of the MEDINFO 2013, 2013
Proceedings of the AMIA 2013, 2013
A Family-Based Framework for Supporting Quality Assurance of Biomedical Ontologies in BioPortal.
Proceedings of the AMIA 2013, 2013
2012
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS.
IEEE J. Solid State Circuits, 2012
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 18th International Conference on Management of Data, 2012
Proceedings of the AMIA 2012, 2012
2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2009
IEEE J. Solid State Circuits, 2009
Proceedings of the Contemporary Computing - Second International Conference, 2009
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008