Sae Kyu Lee

According to our database¹, Sae Kyu Lee authored at least 18 papers between 2009 and 2020.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Other

Links

On csauthors.net:

Bibliography

2020

CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development.

[BibT_eX]

[DOI]

IEEE Micro, 2020

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019

A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

A 16nm 25mm<sup>2</sup> SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET.

[BibT_eX]

[DOI]

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Ares: a framework for quantifying the resilience of deep neural networks.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC-DC Converter.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle.

[BibT_eX]

[DOI]

Pierre-Emile J. Duhamel

Robert J. Wood

David M. Brooks

Gu-Yeon Wei

IEEE J. Solid State Circuits, 2017

14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Sub-uJ deep neural networks for embedded applications.

[BibT_eX]

[DOI]

Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016

A Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter With Four Stacked Output Channels for Voltage Stacking Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

José Miguel Hernández-Lobato

Gu-Yeon Wei

David M. Brooks

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015

A multi-chip system optimized for insect-scale flapping-wing robots.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2015

A 16-core voltage-stacked system with an integrated switched-capacitor DC-DC converter.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2015

2013

Characterizing and evaluating voltage noise in multi-core near-threshold processors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012

Evaluation of voltage stacking for near-threshold multicore computing.

[BibT_eX]

[DOI]

Sae Kyu Lee

David M. Brooks

Gu-Yeon Wei

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

2009

TuneLogic: Post-silicon tuning of dual-Vdd designs.

[BibT_eX]

[DOI]

Stephen Bijansky

Sae Kyu Lee

Adnan Aziz

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Sae Kyu Lee

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...