Ruixue Ding
Orcid: 0009-0006-8632-8032
According to our database1,
Ruixue Ding
authored at least 86 papers
between 2013 and 2025.
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Bibliography
2025
An 8-bit 5-GS/s Single-Channel Hybrid ADC With a λ/4 Transmission Line Based Time Quantizer.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2025
CoRR, August, 2025
IEEE Trans. Circuits Syst. II Express Briefs, July, 2025
A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration.
IEEE Trans. Very Large Scale Integr. Syst., May, 2025
VRAG-RL: Empower Vision-Perception-Based RAG for Visually Rich Information Understanding via Iterative Reasoning with Reinforcement Learning.
CoRR, May, 2025
PIMSR: An Energy-Efficient Processing-in-Memory Accelerator for 60 FPS 4K Super-Resolution.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2025
A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs.
IEEE Trans. Very Large Scale Integr. Syst., March, 2025
ViDoRAG: Visual Document Retrieval-Augmented Generation via Dynamic Iterative Reasoning Agents.
CoRR, February, 2025
A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage.
IEEE J. Solid State Circuits, January, 2025
Microelectron. J., 2025
A 2nd-order delta-sigma capacitance-to-digital converter with an embedded error-feedback exponential-incremental noise-shaping SAR quantizer.
Microelectron. J., 2025
Design and analysis of an ultra-wideband quad-mode quad-core oscillator with mode ambiguity elimination.
Microelectron. J., 2025
Power-efficient SAR ADC with noise-reduction scheme based on kT/C noise cancellation and adaptive tracking averaging.
Microelectron. J., 2025
Rapid digital background calibration of bit weights in pipelined SAR ADC based on multi-PN injection.
Microelectron. J., 2025
A 1-V 3.9-5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and -76-dBc reference spur.
Microelectron. J., 2025
24.2 A 14b 1GS/s Single-Channel Pipelined ADC with A Parallel-Operation SAR Sub-Quantizer and A Dynamic-Deadzone Ring Amplifier.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
Let LLMs Take on the Latest Challenges! A Chinese Dynamic Question Answering Benchmark.
Proceedings of the 31st International Conference on Computational Linguistics, 2025
A 32GS/s 8b 16× Time-Interleaved Hybrid ADC with Self-Detection Offset Calibration, DLL-Based TLSB PVT Variation Calibration and VTC Gain Self-Tracking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
FAPSO: Fast Adaptive Particle Swarm Optimization-Based Background Timing Skew Calibration for TI-ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024
A 182.9-dB FoM 108.2-dB SFDR Power/Bandwidth Configurable Fully Dynamic Switched-Capacitor Zoom ADC With Interstage Leakage Shaping.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024
A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fs<sub>rms</sub> Integrated Jitter and -250.8-dB FOM<sub>PLL</sub>.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
IEEE Trans. Instrum. Meas., 2024
A chopper instrumentation amplifier with discrete-time compensation based on current generation unit to eliminate electrode DC offset.
Microelectron. J., 2024
A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators.
Microelectron. J., 2024
An instrumentation amplifier with series switch pseudo resistor DC-servo loop realizing 0.16-Hz high-pass corner.
Microelectron. J., 2024
An auto-zeroing chopper-stabilized capacitively coupled instrumentation amplifier with 25-Vpp common-mode interference tolerance.
Microelectron. J., 2024
Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS.
Microelectron. J., 2024
Microelectron. J., 2024
A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry.
Microelectron. J., 2024
CoFE-RAG: A Comprehensive Full-chain Evaluation Framework for Retrieval-Augmented Generation with Enhanced Data Diversity.
CoRR, 2024
A 10-GS/s 8-bit 2× time interleaved hybrid ADC with λ/4 reference T-Line sharing technique.
Sci. China Inf. Sci., 2024
MCFC: A Momentum-Driven Clicked Feature Compressed Pre-trained Language Model for Information Retrieval.
Proceedings of the Natural Language Processing and Chinese Computing, 2024
Geo-Encoder: A Chunk-Argument Bi-Encoder Framework for Chinese Geographic Re-Ranking.
Proceedings of the 18th Conference of the European Chapter of the Association for Computational Linguistics, 2024
A 0.0006-mm<sup>2</sup> 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
Proceedings of the Advanced Data Mining and Applications - 20th International Conference, 2024
2023
An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023
IEEE Trans. Very Large Scale Integr. Syst., November, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
16-Cell stackable battery monitoring and management integrated circuit for electric vehicles.
Microelectron. J., 2023
Proceedings of the 46th International ACM SIGIR Conference on Research and Development in Information Retrieval, 2023
A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A $142.8-\mu \text{W}$ 98.1dB-SNDR Power/Bandwidth Configurable Fully Dynamic Discrete-Time Zoom ADC with Interstage Leakage Shaping.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Microelectron. J., 2022
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations.
IEEE J. Solid State Circuits, 2022
Forging Multiple Training Objectives for Pre-trained Language Models via Meta-Learning.
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2022, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Microelectron. J., 2021
A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS.
J. Circuits Syst. Comput., 2021
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021
2020
IEEE Trans. Circuits Syst., 2020
2019
A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC.
J. Circuits Syst. Comput., 2019
Proceedings of the 2019 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies, 2019
Proceedings of the 57th Conference of the Association for Computational Linguistics, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
J. Circuits Syst. Comput., 2018
Inductance of Different Profiles of Through Glass Vias based on magnetic flux density.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
A Background Timing Skew Calibration Technique in Time-Interleaved ADCs With Second Order Compensation.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
A 10-KS/s 625-Hz-Bandwidth 60-dB SNDR Noise-Shaping ADC for Bio-potential Signals Detection Application.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
Event Extraction with Deep Contextualized Word Representation and Multi-attention Layer.
Proceedings of the Advanced Data Mining and Applications - 14th International Conference, 2018
2017
A low-noise programmable gain amplifier with fully balanced differential difference amplifier and class-AB output stage.
Microelectron. J., 2017
2016
Microelectron. J., 2016
Analysis of propagation delay and repeater insertion in single-walled carbon nanotube bundle interconnects.
Microelectron. J., 2016
2015
A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 µm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS.
Microelectron. J., 2015
Strategy for SAR ADC with 87.5% area saving and 99.4% switching energy reduction over conventional approach.
IEICE Electron. Express, 2015
2014
Microelectron. J., 2014
Temperature properties of the parasitic resistance of through-silicon vias (TSVs) in high-frequency 3-D ICs.
IEICE Electron. Express, 2014
2013
Thermo-mechanical performance of Cu and SiO<sub>2</sub> filled coaxial through-silicon-via (TSV).
IEICE Electron. Express, 2013
Analytical models for the thermal strain and stress induced by annular through-silicon-via (TSV).
IEICE Electron. Express, 2013
Reduction of signal reflection in high-frequency three-dimensional (3D) integration circuits.
IEICE Electron. Express, 2013