Sai Pentapati
Orcid: 0000-0003-3966-1749Affiliations:
- Georgia Institute of Technology, Atlanta, GA, USA
According to our database1,
Sai Pentapati
authored at least 22 papers
between 2018 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024
Pin-3D: Effective Physical Design Methodology for Multidie Co-Optimization in Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024
2023
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation.
ACM Trans. Design Autom. Electr. Syst., July, 2023
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Routing Layer Sharing: A New Opportunity for Routing Optimization in Monolithic 3D ICs.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022
2021
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021
ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021
The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021
Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
IEEE Micro, 2019
Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
2018
Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018