Spiridon Nikolaidis

According to our database1, Spiridon Nikolaidis authored at least 85 papers between 1992 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Study of the acoustic noise in pipelines carrying oil products in a refinery establishment.
Proceedings of the 23rd Pan-Hellenic Conference on Informatics, 2019


Pipeline Leak Detection in Noisy Environment.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Improving the Evaluation of the Period and Amplitude of a Signal for Visually Impaired Individuals.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Learnae: Distributed and Resilient Deep Neural Network Training for Heterogeneous Peer to Peer Topologies.
Proceedings of the Engineering Applications of Neural Networks, 2019

2018
A Data-Driven Verilog-A ReRAM Model.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

An Evaluation of the Equivalent Inverter Modeling Approach.
CSSP, 2018

Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS Gates.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Equivalent inverter-based characterization tool for nano-scale CMOS digital cells: Non-linear-delay-models evaluation.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Software design for a sound processing embedded system.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

2017
A compact Verilog-A ReRAM switching model.
CoRR, 2017

An analytical delay model for ReRAM memory cells.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Cache activity profiling tool for the LEON4 processor.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017


Live demonstration: A TiO2 ReRAM parameter extraction method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015
Modeling CMOS Gates Using Equivalent Inverters.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
Real-Time Machine Vision FPGA Implementation for Microfluidic Monitoring on Lab-on-Chips.
IEEE Trans. Biomed. Circuits and Systems, 2014

Design space exploration tools for the ByoRISC configurable processor family.
CoRR, 2014

A unified CMOS inverter model for planar and FinFET nanoscale technologies.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
High performance median FPGA implementation for machine vision applications.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

An efficient model of the CMOS inverter for nanometer technologies.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
FPGA-based machine vision implementation for Lab-on-Chip flow detection.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Estimating the starting point of conduction in nanoscale CMOS gates.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

High speed FPGA implementation of hough transform for real-time applications.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
ILP formulation for hybrid FPGA MPSoCs optimizing performance, area and memory usage.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Design space exploration for FPGA-based multiprocessing systems.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Real-time canny edge detection parallel implementation for FPGAs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators.
IEEE Trans. VLSI Syst., 2009

An Application Development Framework for ARISE Reconfigurable Processors.
TRETS, 2009

Scalable register bypassing for FPGA-based processors.
Microprocess. Microsystems, 2009

Input mapping algorithm for parallel transistor structures.
I. J. Circuit Theory and Applications, 2009

An integer linear programming model for mapping applications on hybrid systems.
IET Computers & Digital Techniques, 2009

2008
Energy Consumption Estimation in Embedded Systems.
IEEE Trans. Instrumentation and Measurement, 2008

Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors.
IEEE Trans. Computers, 2008

ARISE Machines: Extending Processors with Hybrid Accelerators.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Development of a customized processor architecture for accelerating genetic algorithms.
Microprocessors and Microsystems, 2007

Analysing the operation of the basic pass transistor structure.
I. J. Circuit Theory and Applications, 2007

The ARISE Reconfigurable Instruction Set Extensions Framework.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

2006
Measurement of Power Consumption in Digital Systems.
IEEE Trans. Instrumentation and Measurement, 2006

Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications.
J. Low Power Electronics, 2006

A portable specification of zero-overhead looping control hardware applied to embedded processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An automated development framework for a RISC processor with reconfigurable instruction set extensions.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware.
Microprocessors and Microsystems, 2005

Instruction level energy modeling for pipelined processors.
J. Embedded Computing, 2005

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications.
IEICE Transactions, 2005

Developing an environment for embedded software energy estimation.
Comput. Stand. Interfaces, 2005

Energy-Aware System-on-Chip for 5 GHz Wireless LANs.
Proceedings of the Integrated Circuit and System Design, 2005

Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications.
Proceedings of the 2005 Design, 2005

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Measurements analysis of the software-related power consumption in microprocessors.
IEEE Trans. Instrumentation and Measurement, 2004

Evaluating Power Efficient Data-Reuse Decisions For Embedded Multimedia Applications: An Analytical Approach.
Journal of Circuits, Systems, and Computers, 2004

The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms.
Proceedings of the Integrated Circuit and System Design, 2004

Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform.
Proceedings of the Integrated Circuit and System Design, 2004

Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors.
Proceedings of the Integrated Circuit and System Design, 2004

The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems.
Proceedings of the Integrated Circuit and System Design, 2004

Low Power Co-design Tool and Power Optimization of Schedules and Memory System.
Proceedings of the Integrated Circuit and System Design, 2004

An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
Measurement of current variations for the estimation of software-related power consumption [embedded processing circuits].
IEEE Trans. Instrumentation and Measurement, 2003

A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits.
Journal of Circuits, Systems, and Computers, 2003

Tradeoffs in the Design Space Exploration of Application-Specific Processors.
Proceedings of the IFIP VLSI-SoC 2003, 2003

FPGA Architecture Design and Toolset for Logic Implementation.
Proceedings of the Integrated Circuit and System Design, 2003

2002
Efficient output waveform evaluation of a CMOS inverter based on short-circuit current prediction.
I. J. Circuit Theory and Applications, 2002

Output Waveform Evaluation of Basic Pass Transistor Structure.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Instrumentation Set-up for Instruction Level Power Modeling.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Confronting violations of the TSCG(T) in low-power design.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Memory hierarchy exploration for low power architectures in embedded multimedia applications.
Proceedings of the 2001 International Conference on Image Processing, 2001

Analytical exploration of power efficient data-reuse transformations on multimedia applications.
Proceedings of the IEEE International Conference on Acoustics, 2001

2000
Estimation of signal transition activity in FIR filters implementedby a MAC architecture.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

1999
A modeling technique for CMOS gates.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

A Charge Recycling Technique for the Design of Low Power CMOS Clock Drivers.
Journal of Circuits, Systems, and Computers, 1999

Analytical estimation of propagation delay and short‐circuit power dissipation in CMOS gates.
I. J. Circuit Theory and Applications, 1999

CMOS gate modeling based on equivalent inverter.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Analytical Model for the CMOS Short-Circuit Power Dissipation.
Integrated Computer-Aided Engineering, 1998

Accurate calculation of bit-level transition activity using word-level statistics and entropy function.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Collapsing the Transistor Chain to an Effective Single Equivalent Transistor.
Proceedings of the 1998 Design, 1998

Switching Response Modeling of the CMOS Inverter for Sub-micron Devices.
Proceedings of the 1998 Design, 1998

1996
Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1994
Array processor for block adaptive LS FIR filtering.
Signal Processing, 1994

1993
Real time Cepstrum computation based on an Advanced CORDIC processor.
Microprocessing and Microprogramming, 1993

Implementation of Given's Rotation processors for DSP real-time applications.
Microprocessing and Microprogramming, 1993

Development of a technology independent library.
Microprocessing and Microprogramming, 1993

CORDIC Based Pipeline Architecture for All-pass Filters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992
A processor for time-varying digital audio filters with special transition properties.
Proceedings of the Fourth Euromicro workshop on Real-Time Systems, 1992


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