Xrysovalantis Kavousianos

According to our database, Xrysovalantis Kavousianos authored at least 68 papers between 1997 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

K3 TAM Optimization for Testing 3D-SoCs using Non-Regular Time-Division-Multiplexing.

Panagiotis Georgiou, Iakovos Theodosopoulos, Xrysovalantis Kavousianos

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

Testing 3D-SoCs Using 2-D Time-Division Multiplexing.

Panagiotis Georgiou, Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Fault-Independent Test-Generation for Software-Based Self-Testing.

Panagiotis Georgiou, Xrysovalantis Kavousianos, Riccardo Cantoro, Matteo Sonza Reorda

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017

A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-V_dd SoCs.

Fotis Vartziotis, Xrysovalantis Kavousianos, Panagiotis Georgiou, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Critical path - Oriented & thermal aware X-filling for high un-modeled defect coverage.

Fotios Vartziotis, Xrysovalantis Kavousianos

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Two-dimensional time-division multiplexing for 3D-SoCs.

Panagiotis Georgiou, Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

Time-Division Multiplexing for Testing DVFS-Based SoCs.

Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Test-access-mechanism optimization for multi-Vdd SoCs.

Fotios Vartziotis, Xrysovalantis Kavousianos, Panagiotis Georgiou, Krishnendu Chakrabarty

Proceedings of the 2015 IEEE International Test Conference, 2015

A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs.

Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty

Proceedings of the 20th IEEE European Test Symposium, 2015

2014

Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches.

Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas

IEEE Trans. Very Large Scale Integr. Syst., 2014

Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches.

Ran Wang, Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

The Time Dilation Technique for Timing Error Tolerance.

Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos

IEEE Trans. Computers, 2014

Recent advances in single- and multi-site test optimization for DVS-based SoCs.

Xrysovalantis Kavousianos, Krishnendu Chakrabarty

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing.

Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

High-Quality Statistical Test Compression With Narrow ATE Interface.

Vasileios Tenentes, Xrysovalantis Kavousianos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Testing for SoCs with advanced static and dynamic power-management capabilities.

Xrysovalantis Kavousianos, Krishnendu Chakrabarty

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands.

Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Time-division multiplexing for testing SoCs with DVS and multiple voltage islands.

Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets.

Xrysovalantis Kavousianos, Vasileios Tenentes, Krishnendu Chakrabarty, Emmanouil Kalligeros

IEEE Trans. Very Large Scale Integr. Syst., 2011

Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects.

Xrysovalantis Kavousianos, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A Robust and Reconfigurable Multi-mode Power Gating Architecture.

Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A BIST scheme for testing and repair of multi-mode power switches.

Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs.

Vasileios Tenentes, Xrysovalantis Kavousianos

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches.

Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty

Proceedings of the 16th European Test Symposium, 2011

Low Power Test-Compression for High Test-Quality and Low Test-Data Volume.

Vasileios Tenentes, Xrysovalantis Kavousianos

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands.

Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores.

Vasileios Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing.

Vasileios Tenentes, Xrysovalantis Kavousianos

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Self-Freeze Linear Decompressors for Low Power Testing.

Vasileios Tenentes, Xrysovalantis Kavousianos

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Defect aware X-filling for low-power scan testing.

S. Balatsouka, Vasileios Tenentes, Xrysovalantis Kavousianos, Krishnendu Chakrabarty

Proceedings of the Design, Automation and Test in Europe, 2010

Defect Coverage-Driven Window-Based Test Compression.

Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Emmanouil Kalligeros, Vasileios Tenentes

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Efficient partial scan cell gating for low-power scan-based testing.

Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos

ACM Trans. Design Autom. Electr. Syst., 2009

LFSR-based test-data compression with self-stoppable seeds.

M. Koutsoupia, Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos

Proceedings of the Design, Automation and Test in Europe, 2009

Generation of compact test sets with high defect coverage.

Xrysovalantis Kavousianos, Krishnendu Chakrabarty

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains.

Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos

IEEE Trans. Very Large Scale Integr. Syst., 2008

Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability.

Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Timing Error Detection and Correction by Time Dilation.

Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos

Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores.

Vasileios Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores.

Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Optimal Selective Huffman Coding for Test-Data Compression.

Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos

IEEE Trans. Computers, 2007

2006

Efficient Multiphase Test Set Embedding for Scan-based Testing.

Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Efficient test-data compression for IP cores using multilevel Huffman coding.

Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Reseeding-Based Test Set Embedding with Reduced Test Sequences.

Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Power aware test-data compression for scan-based testing.

George Gekas, Dimitris Nikolos, Emmanouil Kalligeros, Xrysovalantis Kavousianos

Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004

Multiphase BIST: a new reseeding technique for high test-data compression.

Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

An Efficient Test Vector Ordering Method for Low Power Testing.

Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Low Power Testing by Test Vector Ordering with Vector Repetition.

Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2003

DV-TSE: Difference Vector Based Test Set Embedding.

Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris

Proceedings of the IFIP VLSI-SoC 2003, 2003

Virtual-scan: a novel approach for software-based self-testing of microprocessors.

Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A highly regular multi-phase reseeding technique for scan-based BIST.

Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002

A new built-in TPG method for circuits with random patternresistant faults.

Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST.

Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos

J. Electron. Test., 2002

An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST.

Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

A ROMless LFSR Reseeding Scheme for Scan-based BIST.

Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Low Power Built-In Self-Test Schemes for Array and Booth Multipliers.

Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou

VLSI Design, 2001

On Accumulator-Based Bit-Serial Test Response Compaction Schemes.

Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

On the Design of Self-Testing Checkers for Modified Berger Codes.

Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A New Reseeding Technique for LFSR-Based Test Pattern Generation.

Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A novel reseeding technique for accumulator-based test pattern generation.

Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000

Σχεδίαση αυτοελεγχόμενων ελεγκτών σε τεχνολογία VLSI

Xrysovalantis Kavousianos

PhD thesis, 2000

Novel Single and Double Output TSC CMOS Checkers for <i>m</i>-out-of-<i>n</i> Codes.

Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos

VLSI Design, 2000

Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register.

Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

New efficient totally self-checking Berger code checkers.

Xrysovalantis Kavousianos, Dimitris Nikolos, G. Foukarakis, T. Gnardellis

Integr., 1999

Modular TSC Checkers for Bose-Lin and Bose Codes.

Xrysovalantis Kavousianos, Dimitris Nikolos

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Low Power Dissipation in BIST Schemes for Modified Booth Multipliers.

Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998

Novel Single and Double Output TSC Berger Code Checkers.

Xrysovalantis Kavousianos, Dimitris Nikolos

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997

Self-exercising self testing k-order comparators.

Xrysovalantis Kavousianos, Dimitris Nikolos

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes.

Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997