Younghun Seo
Orcid: 0000-0003-3079-0843
According to our database1,
Younghun Seo authored at least 10 papers
between 2017 and 2026.
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Bibliography
2026
IEEE Signal Process. Lett., 2026
15.10 A Vertical-Cell-Transistor-Based 4F<sup>2</sup> DRAM with Cell-on-Peripheral Architecture Using Wafer-to-Wafer Hybrid Copper Bonding.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A 16Gb 12.8Gb/s LPDDR6 SDRAM with 12-DQ/Sub-Channel Wide NRZ Signaling and Enhanced Reliability by Per-Row Activation Counting and Meta-Data Scheme.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
IEEE J. Solid State Circuits, April, 2025
2024
An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2019
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
IEEE J. Solid State Circuits, 2019
Optimum Modulation Orders for 1-bit Compressively Sampled Signals in Multicarrier Transmission.
Proceedings of the 20th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2019
2018
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017