Miriam Leeser
Orcid: 0000-0002-5624-056XAffiliations:
- Northeastern University, Boston, USA
According to our database1,
Miriam Leeser
authored at least 169 papers
between 1986 and 2024.
Collaborative distances:
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on orcid.org
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on coe.neu.edu
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Bibliography
2024
Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function.
Sensors, March, 2024
EdgeQAT: Entropy and Distribution Guided Quantization-Aware Training for the Acceleration of Lightweight LLMs on the Edge.
CoRR, 2024
2023
ACM Trans. Reconfigurable Technol. Syst., September, 2023
CoRR, 2023
A Framework to Enable Runtime Programmable P4-enabled FPGAs in the Open Cloud Testbed.
Proceedings of the IEEE INFOCOM 2023, 2023
Selective Encryption of Compressed Image Regions on the Edge with Reconfigurable Hardware.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023
Accelerating Garbled Circuits in the Open Cloud Testbed with Multiple Network-Attached FPGAs.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023
Neural Network on the Edge: Efficient and Low Cost FPGA Implementation of Digital Predistortion in MIMO Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
ACM Trans. Reconfigurable Technol. Syst., 2022
IEEE Des. Test, 2022
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
Proceedings of the IEEE INFOCOM 2022, 2022
Hardware Software Codesign of Applications on the Edge: Accelerating Digital PreDistortion for Wireless Communications.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022
Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach.
IEEE Trans. Computers, 2021
Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021
Computationally Efficient Look-up-Tables for Behavioral Modelling and Digital Pre-distortion of Multi-standard Wireless Systems.
Proceedings of the Cognitive Radio Oriented Wireless Networks and Wireless Internet, 2021
Proceedings of the 10th IEEE International Conference on Cloud Networking, CloudNet 2021, 2021
2020
Strategies and Demonstration to Support Multiple Wireless Protocols with a Single RF Front-End.
IEEE Wirel. Commun., 2020
A Novel Physical Layer Authentication With PAPR Reduction Based on Channel and Hardware Frequency Responses.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
High-performance transformation of protein structure representation from internal to Cartesian coordinates.
J. Comput. Chem., 2020
IEEE Access, 2020
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020
Exploiting GPU Direct Access to Non-Volatile Memory to Accelerate Big Data Processing.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Demonstrating Spectrally Efficient Asynchronous Coexistence for Machine Type Communication: A Software Defined Radio Approach.
Proceedings of the Cognitive Radio-Oriented Wireless Networks, 2020
2019
ACM Trans. Model. Comput. Simul., 2019
Math. Comput. Simul., 2019
ACM J. Emerg. Technol. Comput. Syst., 2019
Int. J. Reconfigurable Comput., 2019
An FPGA Design Technique to Receive Multiple Wireless Protocols with the Same RF Front End.
Proceedings of the 2019 Wireless Days, 2019
Proceedings of the 2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, 2019
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019
2018
FINN-<i>R</i>: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks.
ACM Trans. Reconfigurable Technol. Syst., 2018
IEEE Trans. Emerg. Top. Comput., 2018
Local and Global Shared Memory for Task Based HPC Applications on Heterogeneous Platforms.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018
Dynamic Deployment of Communication Applications to Different Hardware Platforms using Ontological Representations.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
Proceedings of the Cognitive Radio Oriented Wireless Networks, 2018
Detection of Different Wireless Protocols on an FPGA with the Same Analog/RF Front End.
Proceedings of the Cognitive Radio Oriented Wireless Networks, 2018
2017
A Framework for Developing Parallel Applications with high level Tasks on Heterogeneous Platforms.
Proceedings of the 8th International Workshop on Programming Models and Applications for Multicores and Manycores, 2017
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Accelerating big data applications using lightweight virtualization framework on enterprise cloud.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017
Using High Level GPU Tasks to Explore Memory and Communications Options on Heterogeneous Platforms.
Proceedings of the 2017 Workshop on Software Engineering Methods for Parallel and High Performance Applications, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
FIM: Performance Prediction for Parallel Computation in Iterative Data Processing Applications.
Proceedings of the 2017 IEEE 10th International Conference on Cloud Computing (CLOUD), 2017
2016
ACM Trans. Reconfigurable Technol. Syst., 2016
High-Level System Design of IEEE 802.11b Standard-Compliant Link Layer for MATLAB-Based SDR.
IEEE Access, 2016
Proceedings of the 10th International Symposium on Medical Information and Communication Technology, 2016
Performance prediction techniques for scalable large data processing in distributed MPI systems.
Proceedings of the 35th IEEE International Performance Computing and Communications Conference, 2016
High-level hardware-software co-design of an 802.11a transceiver system using Zynq SoC.
Proceedings of the IEEE Conference on Computer Communications Workshops, 2016
Unified and lightweight tasks and conduits: A high level parallel programming framework.
Proceedings of the 2016 IEEE High Performance Extreme Computing Conference, 2016
Design space exploration of GPU Accelerated cluster systems for optimal data transfer using PCIe bus.
Proceedings of the 2016 IEEE High Performance Extreme Computing Conference, 2016
Modeling considerations for the hardware-software co-design of flexible modern wireless transceivers.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Proceedings of the International Conference on Distributed Computing in Sensor Systems, 2016
2015
IEEE Trans. Parallel Distributed Syst., 2015
IACR Cryptol. ePrint Arch., 2015
Leakage evaluation on power balance countermeasure against side-channel attack on FPGAs.
Proceedings of the 2015 IEEE High Performance Extreme Computing Conference, 2015
Proceedings of the 2015 IEEE High Performance Extreme Computing Conference, 2015
Proceedings of the 2015 IEEE High Performance Extreme Computing Conference, 2015
Proceedings of the Euro-Par 2015: Parallel Processing, 2015
Proceedings of the Cognitive Radio Oriented Wireless Networks, 2015
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015
2014
IACR Cryptol. ePrint Arch., 2014
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Digital Logic.
Proceedings of the Computing Handbook, 2014
2013
Kernel Specialization for Improved Adaptability and Performance on Graphics Processing Units (GPUs).
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013
FPGA-based hyperspectral covariance coprocessor for size, weight, and power constrained platforms.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2013
Vendor agnostic, high performance, double precision Floating Point division for FPGAs.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2013
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
2012
Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
VForce: An environment for portable applications on high performance systems with accelerators.
J. Parallel Distributed Comput., 2012
Proceedings of the IEEE Conference on High Performance Extreme Computing, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
2011
SIGARCH Comput. Archit. News, 2011
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011
2010
VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware.
ACM Trans. Reconfigurable Technol. Syst., 2010
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010
2009
ACM Trans. Embed. Comput. Syst., 2009
FPGA Supercomputing Platforms, Architectures, and Techniques for Accelerating Computationally Complex Algorithms.
EURASIP J. Embed. Syst., 2009
EURASIP J. Embed. Syst., 2009
The Effect of Parameterization on a Reconfigurable Implementation of PIV.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA.
Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, 2009
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009
2008
Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2008
J. Parallel Distributed Comput., 2008
Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison.
Proceedings of the 2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications, 2008
Efficient FPGA implementation of qr decomposition using a systolic array architecture.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008
2007
J. Real Time Image Process., 2007
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007
Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007
The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency.
IEEE Trans. Multim., 2006
J. Aerosp. Comput. Inf. Commun., 2006
Poster reception - Improving the performance of parallel backprojection on a reconfigurable supercomputer.
Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006
Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006
Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006
2005
J. VLSI Signal Process., 2005
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
2004
An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004
Dynamo: A Runtime Partitioning System.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004
2003
Proceedings of the Eleventh ACM International Conference on Multimedia, 2003
Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003
Precision Modeling of Floating-Point Applications for Variable Bitwidth Computing.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003
2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002
2001
VLSI Design, 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Implementing a RAKE receiver for wireless communications on an FPGA-based computer system.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000
1998
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998
Proceedings of the 35th Conference on Design Automation, 1998
1997
Proceedings of the Fifth ACM International Conference on Multimedia '97, 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997
1996
Area and Performance Tradeoffs in Floating-Point Divide and Square-Root Implementations.
ACM Comput. Surv., 1996
1995
Verifying a Logic-Synthesis Algorithm and Implementation: A Case Study in Software Verification.
IEEE Trans. Software Eng., 1995
IEEE Trans. Computers, 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995
1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization.
Proceedings of the Theorem Provers in Circuit Design, 1994
Proceedings of the Theorem Provers in Circuit Design, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
1993
J. VLSI Signal Process., 1993
J. VLSI Signal Process., 1993
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
HML: A Hardware Description Language Based on Standard ML.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993
1992
A Methodology for Reusable Hardware Proofs.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1992
Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992
1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1989
Reasoning about the function and timing of integrated circuits with interval temporal logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
Proceedings of the Hardware Specification, 1989
1987
Reasoning about the function and timing of integrated circuits with Prolog and temporal logic.
PhD thesis, 1987
1986
Integr., 1986