Giuseppe Ascia

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

A Study on Evolutionary Multi-Objective Optimization with Fuzzy Approximation for Computational Expensive Problems.

[BibT_eX]

[DOI]

Proceedings of the Parallel Problem Solving from Nature - PPSN XII, 2012

2011

Data Encoding Schemes in Networks on Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems.

[BibT_eX]

[DOI]

Appl. Soft Comput., 2011

2009

Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

2007

Efficient design space exploration for application specific systems-on-a-chip.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

2006

An integrated fuzzy-GA approach for buffer management.

[BibT_eX]

[DOI]

IEEE Trans. Fuzzy Syst., 2006

A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2006

An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design.

[BibT_eX]

[DOI]

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Neighbors-on-Path: A New Selection Strategy for On-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

Fuzzy decision making in embedded system design.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

2005

An evolutionary management scheme in high-performance packet switches.

[BibT_eX]

[DOI]

IEEE/ACM Trans. Netw., 2005

A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Hyperblock formation: a power/energy perspective for high performance VLIW architectures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An evolutionary approach to network-on-chip mapping problem.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2005

A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Exploring Design Space of VLIW Architectures.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

A GA-based design space exploration framework for parameterized system-on-a-chip platforms.

[BibT_eX]

[DOI]

IEEE Trans. Evol. Comput., 2004

Multi-objective Optimization of a Parameterized VLIW Architecture.

[BibT_eX]

[DOI]

Proceedings of the 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 2004

Multi-objective mapping for mesh-based NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

A Genetic Approach To Bus Encoding.

[BibT_eX]

Proceedings of the IFIP VLSI-SoC 2003, 2003

A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

An evolutionary approach for reducing the energy in address buses.

[BibT_eX]

[DOI]

Proceedings of the 1st Intenational Symposium on Information and Communication Technologies, 2003

EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration.

[BibT_eX]

Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

An evolutionary approach for reducing the switching activity in address buses.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2003

2002

A Framework for Design Space Exploration of Parameterized VLSI Systems.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

An efficient buffer management policy based on an integrated Fuzzy-GA approach.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE INFOCOM 2002, 2002

2001

An Instruction-Level Power Analysis Model with Data Dependency.

[BibT_eX]

[DOI]

VLSI Design, 2001

An efficient fuzzy system for traffic management in high-speed packet-switched networks.

[BibT_eX]

[DOI]

Soft Comput., 2001

An adaptive fuzzy threshold scheme for high performance shared-memory switches.

[BibT_eX]

[DOI]

Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), 2001

A Fuzzy Buffer Management Scheme For ATM and IP Networks.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE INFOCOM 2001, 2001

An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms.

[BibT_eX]

Proceedings of the SOC Design Methodologies, 2001

A General Purpose Processor Oriented Fuzzy Reasoning.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Conference on Fuzzy Systems, 2001

Parameterised system design based on genetic algorithms.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000

A pipeline parallel architecture for a fuzzy inference processor.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International Conference on Fuzzy Systems, 2000

1999

VLSI hardware architecture for complex fuzzy systems.

[BibT_eX]

[DOI]

Marco Russo

IEEE Trans. Fuzzy Syst., 1999

An Optimized Parallel RISC Processor for Fuzzy Computing.

[BibT_eX]

Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1998

A Framework for a Parallel Architecture Dedicated to Soft Computing.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997

A VLSI fuzzy expert system for real-time traffic control in ATM networks.

[BibT_eX]

[DOI]

IEEE Trans. Fuzzy Syst., 1997

Design of a VLSI Hardware PET Decoder.

[BibT_eX]

[DOI]

Giuseppe Ficili

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

A Reconfigurable Parallel Architecture for a Fuzzy Processor.

[BibT_eX]

[DOI]

Inf. Sci., 1996

An Efficient Hardware Architecture to Support Complex Fuzzy Reasoning.

[BibT_eX]

[DOI]

Int. J. Artif. Intell. Tools, 1996

1995

Fuzzy Hardware Challenges.

[BibT_eX]

[DOI]

Andrés Jaramillo-Botero

IEEE Micro, 1995

Designing for parallel fuzzy computing.

[BibT_eX]

[DOI]

IEEE Micro, 1995

A VLSI Parallel Architecture for Fuzzy Expert Systems.

[BibT_eX]

[DOI]

Int. J. Pattern Recognit. Artif. Intell., 1995

Design of a VLSI parallel processor for fuzzy computing.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Design of a VLSI fuzzy processor for ATM traffic sources management.

[BibT_eX]

[DOI]

Giuseppe Ficili