Leandro Fiorin

According to our database1, Leandro Fiorin authored at least 30 papers between 2007 and 2018.

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Bibliography

2018
Near-Memory Acceleration for Radio Astronomy.
IEEE Trans. Parallel Distrib. Syst., 2018

2017
An Architecture for Integrated Near-Data Processors.
TACO, 2017

Boosting the Efficiency of HPCG and Graph500 with Near-Data Processing.
Proceedings of the 46th International Conference on Parallel Processing, 2017

MeSAP: A fast analytic power model for DRAM memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Sorting big data on heterogeneous near-data processing systems.
Proceedings of the Computing Frontiers Conference, 2017

2016
Exploring the Design Space of an Energy-Efficient Accelerator for the SKA1-Low Central Signal Processor.
International Journal of Parallel Programming, 2016

An architecture for near-data processing systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Challenges in exascale radio astronomy: Can the SKA ride the technology wave?
IJHPCA, 2015

An energy-efficient custom architecture for the SKA1-low central signal processor.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
A Configurable Monitoring Infrastructure for NoC-Based Architectures.
IEEE Trans. VLSI Syst., 2014

Fault-Tolerant Network Interfaces for Networks-on-Chip.
IEEE Trans. Dependable Sec. Comput., 2014

Exascale Radio Astronomy: Can We Ride the Technology Wave?
Proceedings of the Supercomputing - 29th International Conference, 2014

Towards a Reliability-aware Design Flow for Kahn Process Networks on NoC-based Multiprocessors.
Proceedings of the ARCS 2014, 2014

2013
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.
Microprocess. Microsystems, 2013

2012
System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Security Enhanced Linux on embedded systems: A hardware-accelerated implementation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips.
Int. J. Reconfig. Comp., 2011

Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors.
Proceedings of the NOCS 2011, 2011

Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Design of Fault Tolerant Network Interfaces for NoCs.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
A monitoring system for NoCs.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

Stack protection unit as a step towards securing MPSoCs.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Hardware-assisted security enhanced Linux in embedded systems: a proposal.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

2009
MPSoCs run-time monitoring through Networks-on-Chip.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Secure Memory Accesses on Networks-on-Chip.
IEEE Trans. Computers, 2008

An Automated Design Flow for NoC-based MPSoCs on FPGA.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

Implementation of a reconfigurable data protection module for NoC-based MPSoCs.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A security monitoring service for NoCs.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007
Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A data protection unit for NoC-based architectures.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007


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