Eric Flamand
According to our database1,
Eric Flamand
authored at least 22 papers
between 2009 and 2023.
Collaborative distances:
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Bibliography
2023
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
CoRR, 2023
2022
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
IEEE J. Solid State Circuits, 2022
Accelerating RNN-Based Speech Enhancement on a Multi-core MCU with Mixed FP16-INT8 Post-training Quantization.
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2022
2021
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
CoRR, 2021
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Integer-Only Approximated MFCC for Ultra-Low Power Audio NN Processing on Multi-Core MCUs.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2019
IEEE Internet Things J., 2019
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Always-ON visual node with a hardware-software event-based binarized neural network inference engine.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
2016
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2013
A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory.
Proceedings of the International Conference on Compilers, 2013
2012
Proceedings of the 2012 Interconnection Network Architecture, 2012
P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011
2009
Proceedings of the Design, Automation and Test in Europe, 2009