Jianan Mu

According to our database, Jianan Mu authored at least 19 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

FicGCN: Unveiling the Homomorphic Encryption Efficiency from Irregular Graph Convolutional Networks.

Zhaoxuan Kan, Husheng Han, Shangyi Shi, Tenghui Hua, Hang Lu, Xiaowei Li, Jianan Mu, Xing Hu

CoRR, June, 2025

Large Processor Chip Model.

Kaiyan Chang, Mingzhi Chen, Yunji Chen, Zhirong Chen, Dongrui Fan, Junfeng Gong, Nan Guo, Yinhe Han, Qinfen Hao, Shuo Hou, Xuanjing Huang, Pengwei Jin, Changxin Ke, Cangyuan Li, Guangli Li, Huawei Li, Kuan Li, Naipeng Li, Shengwen Liang, Cheng Liu, Hongwei Liu, Jiahua Liu, Junliang Lv, Jianan Mu, Jin Qin, Bin Sun, Chenxi Wang, Duo Wang, Mingjun Wang, Ying Wang, Chenggang Wu, Peiyang Wu, Teng Wu, Xiao Xiao, Mengyao Xie, Chenwei Xiong, Ruiyuan Xu, Mingyu Yan, Xiaochun Ye, Kuai Yu, Rui Zhang, Shuoming Zhang, Jiacheng Zhao

CoRR, June, 2025

CodeV-R1: Reasoning-Enhanced Verilog Generation.

Yaoyu Zhu, Di Huang, Han-Qi Lyu, Xiaoyun Zhang, Chongxiao Li, Wenxuan Shi, Yutong Wu, Jianan Mu, Jinghua Wang, Yang Zhao, Pengwei Jin, Shuyao Cheng, Shengwen Liang, Xishan Zhang, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen

CoRR, May, 2025

Extend IVerilog to Support Batch RTL Fault Simulation.

Jiaping Tang, Jianan Mu, Zizhen Liu, Zhiteng Chao, Jing Ye, Huawei Li

CoRR, May, 2025

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy.

Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shenwen Liang, Jing Ye, Huawei Li, Xiaowei Li

CoRR, April, 2025

FlexMem: High-Parallel Near-Memory Architecture for Flexible Dataflow in Fully Homomorphic Encryption.

Shangyi Shi, Husheng Han, Jianan Mu, Xinyao Zheng, Ling Liang, Hang Lu, Zidong Du, Xiaowei Li, Xing Hu, Qi Guo

CoRR, March, 2025

HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion.

Zhiteng Chao, Bin Sun, Hongqin Lyu, Ge Yu, Minjun Wang, Wenxing Li, Zizhen Liu, Jianan Mu, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li

Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy.

Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li

Proceedings of the Design, Automation & Test in Europe Conference, 2025

ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring.

Mingjun Wang, Hui Wang, Zizhen Liu, Feng Gu, Jianan Mu, Jiaping Tang, Jun Gao, Huawei Li, Jing Ye, Xiaowei Li

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262.

Mingjun Wang, Hui Wang, Jianan Mu, Zizhen Liu, Jun Gao, Jing Ye, Huawei Li, Xiaowei Li

Proceedings of the IEEE International Test Conference in Asia, 2024

DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism.

Feng Gu, Mingjun Wang, Jianan Mu, Zizhen Liu, Jiaping Tang, Hui Wang, Yonghao Wang, Jing Ye, Huawei Li, Xiaowei Li

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption.

Jianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen Liu, Shengwen Liang, Meng Li, Mingzhe Zhang, Song Bian, Xing Hu, Huawei Li, Xiaowei Li

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction.

Jiaping Tang, Zizhen Liu, Jianan Mu, Feng Gu, Mingjun Wang, Wenxing Li, Jing Ye, Xiaowei Li, Huawei Li

Proceedings of the 33rd IEEE Asian Test Symposium, 2024

TensorTEE: Unifying Heterogeneous TEE Granularity for Efficient Secure Collaborative Tensor Computing.

Husheng Han, Xinyao Zheng, Yuanbo Wen, Yifan Hao, Erhu Feng, Ling Liang, Jianan Mu, Xiaqing Li, Tianyun Ma, Pengwei Jin, Xinkai Song, Zidong Du, Qi Guo, Xing Hu

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023

Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.

Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants.

Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li

Proceedings of the IEEE European Test Symposium, 2023

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array.

Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design.

Jianan Mu, Huajie Tan, Shuai Chen, Min Cai, Jing Ye, Huawei Li, Xiaowei Li

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022

A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber.

Jianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022