Jochen Rivoir

According to our database, Jochen Rivoir authored at least 22 papers between 2001 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Deep Feature Selection Using a Novel Complementary Feature Mask.

Yiwen Liao, Jochen Rivoir, Raphaël Latty, Bin Yang

CoRR, 2022

A Deep-Learning-Aided Pipeline for Efficient Post-Silicon Tuning.

Yiwen Liao, Bin Yang, Raphaël Latty, Jochen Rivoir

CoRR, 2022

Intelligent Methods for Test and Reliability.

Hussam Amrouch, Jens Anders, Steffen Becker, Maik Betka, Gerd Bleher, Peter Domanski, Nourhan Elhamawy, Thomas Ertl, Athanasios Gatzastras, Paul R. Genssler, Sebastian Hasler, Martin Heinrich, André van Hoorn, Hanieh Jafarzadeh, Ingmar Kallfass, Florian Klemme, Steffen Koch, Ralf Küsters, Andrés Lalama, Raphaël Latty, Yiwen Liao, Natalia Lylina, Zahra Paria Najafi-Haghi, Dirk Pflüger, Ilia Polian, Jochen Rivoir, Matthias Sauer, Denis Schwachhofer, Steffen Templin, Christian Volmer, Stefan Wagner, Daniel Weiskopf, Hans-Joachim Wunderlich, Bin Yang, Martin Zimmermann

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Self-Learning Tuning for Post-Silicon Validation.

Peter Domanski, Dirk Pflüger, Jochen Rivoir, Raphaël Latty

CoRR, 2021

ORSA: Outlier Robust Stacked Aggregation for Best- and Worst-Case Approximations of Ensemble Systems.

Peter Domanski, Dirk Pflüger, Raphaël Latty, Jochen Rivoir

Proceedings of the 20th IEEE International Conference on Machine Learning and Applications, 2021

2019

IP Session on Machine Learning Applications in IC Test-Related Tasks.

Ghada Sokar, Yassin Zakaria, Asmaa Rabie, Kareem Madkour, Ira Leventhal, Jochen Rivoir, Xinli Gu, Haralampos-G. D. Stratigopoulos

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2018

Efficient generation of parametric test conditions for AMS chips with an interval constraint solver.

Felix Neubauer, Jan Burchard, Pascal Raiola, Jochen Rivoir, Bernd Becker, Matthias Sauer

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2011

A Level-Crossing Approach for the Analysis of RF Modulated Signals Using Only Digital Test Resources.

Nicolas Pous, Florence Azaïs, Laurent Latorre, Jochen Rivoir

J. Electron. Test., 2011

2010

Experiments on the analysis of phase/frequency-modulated RF signals using digital tester channels.

Nicolas Pous, Florence Azaïs, Laurent Latorre, Pascal Nouet, Jochen Rivoir

Proceedings of the 11th Latin American Test Workshop, 2010

On the use of standard digital ATE for the analysis of RF signals.

Nicolas Pous, Florence Azaïs, Laurent Latorre, Jochen Rivoir

Proceedings of the 15th European Test Symposium, 2010

2009

Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE.

Nicolas Pous, Florence Azaïs, Laurent Latorre, Pascal Nouet, Jochen Rivoir

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2007

Fast and Low Cost HW Bit Map for Memory Test Based on Residue Polynomial System over GF(2).

Jochen Rivoir

Proceedings of the 16th Asian Test Symposium, 2007

Special Session: Analog Production Test.

Fidel Muradali, Jochen Rivoir

Proceedings of the 16th Asian Test Symposium, 2007

2006

Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration.

Jochen Rivoir

Proceedings of the 2006 IEEE International Test Conference, 2006

Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator.

Jochen Rivoir

Proceedings of the 15th Asian Test Symposium, 2006

2004

Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE Channel.

Jochen Rivoir

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits.

Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus-Dieter Hilliges

J. Electron. Test., 2003

Lowering Cost of Test: Parallel Test or Low-Cost ATE?

Jochen Rivoir

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Test Economics for Multi-site Test with Modern Cost Reduction Techniques.

Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus-Dieter Hilliges

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Test Vector Compression Using EDA-ATE Synergies.

Ajay Khoche, Erik H. Volkerink, Jochen Rivoir, Subhasish Mitra

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2001

Tackling test trade-offs from design, manufacturing to market using economic modeling.

Erik H. Volkerink, Ajay Khoche, Linda A. Kamas, Jochen Rivoir, Hans G. Kerkhoff

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A new methodology for improved tester utilization.

Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001