Laurent Brunet

According to our database1, Laurent Brunet authored at least 10 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2018
A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2017
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices.
Proceedings of the 47th European Solid-State Device Research Conference, 2017


2016


Impact of intermediate BEOL technology on standard cell performances of 3D VLSI.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2014
FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration.
Proceedings of the 44th European Solid State Device Research Conference, 2014


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