Liang Shi
Orcid: 0000-0002-9977-529XAffiliations:
- East China Normal University, Shanghai, China
According to our database1,
Liang Shi
authored at least 151 papers
between 2010 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
Prophet: SSD Failure Analysis and Prediction Guided by Flash Reliability Characteristics in Data Centers.
IEEE Trans. Computers, August, 2025
IEEE Trans. Very Large Scale Integr. Syst., June, 2025
Freezing-based Memory and Process Co-design for User Experience on Resource-limited Mobile Devices.
ACM Trans. Comput. Syst., 2025
Breathing new life into compression: Resolving the dilemma of LFS with compression on flash storage.
J. Syst. Archit., 2025
Proceedings of the 2025 USENIX Annual Technical Conference, 2025
Proceedings of the Design, Automation & Test in Europe Conference, 2025
Simplifying and Accelerating NOR Flash I/O Stack for RAM-Restricted Microcontrollers.
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
MTPS: A Multi-Task Perceiving and Scheduling Framework Across Multiple Mobile Devices.
IEEE Trans. Mob. Comput., December, 2024
ACM Trans. Archit. Code Optim., December, 2024
Introduction to Special Issue on In/Near Memory and Storage Computing for Embedded Systems.
ACM Trans. Embed. Comput. Syst., November, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024
IEEE Internet Things J., May, 2024
ACM Trans. Archit. Code Optim., March, 2024
IEEE Trans. Parallel Distributed Syst., January, 2024
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories.
ACM Trans. Design Autom. Electr. Syst., January, 2024
Adaptive Differential Wearing for Read Performance Optimization on High-Density nand Flash Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
Hook: A Pattern Locality Guided Prefetch with Enhanced Read Performance for Hybrid SSDs.
Proceedings of the 13th Non-Volatile Memory Systems and Applications Symposium, 2024
Eliminate Critical Fragmentation of F2FS in Mobile Devices with Controller Co-Design.
Proceedings of the 13th Non-Volatile Memory Systems and Applications Symposium, 2024
Proceedings of the International Conference on Networking, Architecture and Storage, 2024
CacheTrimmer: Adaptive Cache File Trimming for Optimized Performance and Lifetime on Mobile Devices.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
IOSR: Improving I/O Efficiency for Memory Swapping on Mobile Devices Via Scheduling and Reshaping.
ACM Trans. Embed. Comput. Syst., October, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
J. Syst. Archit., March, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the 15th ACM/USENIX Workshop on Hot Topics in Storage and File Systems, 2023
ICE: Collaborating Memory and Process Management for User Experience on Resource-limited Mobile Devices.
Proceedings of the Eighteenth European Conference on Computer Systems, 2023
DECC: Differential ECC for Read Performance Optimization on High-Density NAND Flash Memory.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
CCF Trans. High Perform. Comput., December, 2022
Editorial for the special issue on memory architectures and systems for modern applications.
CCF Trans. High Perform. Comput., December, 2022
Tail Latency Optimization for LDPC-Based High-Density and Low-Cost Flash Memory Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Read latency variation aware performance optimization on high-density NAND flash based storage systems.
CCF Trans. High Perform. Comput., 2022
Access Characteristic Guided Remote Swapping for User Experience Optimization on Mobile Devices.
Proceedings of the IEEE Smartworld, 2022
Proceedings of the 11th IEEE Non-Volatile Memory Systems and Applications Symposium, 2022
Proceedings of the 11th IEEE Non-Volatile Memory Systems and Applications Symposium, 2022
DWR: Differential Wearing for Read Performance Optimization on High-Density NAND Flash Memory.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
CDB: critical data backup design for consumer devices with high-density flash based hybrid storage.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Read-Ahead Efficiency on Mobile Devices: Observation, Characterization, and Optimization.
IEEE Trans. Computers, 2021
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Dynamic File Cache Optimization for Hybrid SSDs with High-Density and Low-Cost Flash Memory.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Pattern-Guided File Compression with User-Experience Enhancement for Log-Structured File System on Mobile Devices.
Proceedings of the 19th USENIX Conference on File and Storage Technologies, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Process Variation Aware Read Performance Improvement for LDPC-Based nand Flash Memory.
IEEE Trans. Reliab., 2020
IEEE Trans. Parallel Distributed Syst., 2020
ACM Trans. Storage, 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Maximizing I/O Throughput and Minimizing Performance Variation via Reinforcement Learning Based I/O Merging for SSDs.
IEEE Trans. Computers, 2020
IEEE Trans. Computers, 2020
Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems.
J. Syst. Archit., 2020
Proceedings of the 2020 USENIX Annual Technical Conference, 2020
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Proceedings of the 9th Non-Volatile Memory Systems and Applications Symposium, 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Latency Variation Aware Read Performance Optimization on 3D High Density NAND Flash Memory.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Access Characteristic Guided Partition for Read Performance Improvement on Solid State Drives.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
IEEE Trans. Mob. Comput., 2019
Minimizing Retention Induced Refresh Through Exploiting Process Variation of Flash Memory.
IEEE Trans. Computers, 2019
SIGBED Rev., 2019
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019
Proceedings of the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, 2019
Optimizing Tail Latency of LDPC based Flash Memory Storage Systems Via Smart Refresh.
Proceedings of the 2019 IEEE International Conference on Networking, 2019
Parallel all the time: Plane Level Parallelism Exploration for High Performance SSDs.
Proceedings of the 35th Symposium on Mass Storage Systems and Technologies, 2019
Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019
Proceedings of the 11th USENIX Workshop on Hot Topics in Storage and File Systems, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
ACM Trans. Storage, 2018
Exploiting Chip Idleness for Minimizing Garbage Collection - Induced Chip Access Conflict on SSDs.
ACM Trans. Design Autom. Electr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Access Characteristic Guided Read and Write Regulation on Flash Based Storage Systems.
IEEE Trans. Computers, 2018
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Loss is Gain: Shortening Data for Lifetime Improvement on Low-Cost ECC Enabled Consumer-Level Flash Memory.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Revisiting wear leveling design on compression applied 3D NAND flash memory: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
ACM Trans. Embed. Comput. Syst., 2017
Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Microprocess. Microsystems, 2017
Improving File System Performance of Mobile Storage Systems Using a Decoupled Defragmenter.
Proceedings of the 2017 USENIX Annual Technical Conference, 2017
Proceedings of the 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2017
Improving read performance via selective Vpass reduction on high density 3D NAND flash memory.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017
Exploiting Process Variation for Read Performance Improvement on LDPC Based Flash Memory Storage Systems.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement.
Proceedings of the 54th Annual Design Automation Conference, 2017
A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
J. Signal Process. Syst., 2016
Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Computers, 2016
J. Syst. Archit., 2016
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016
Minimizing cell-to-cell interference by exploiting differential bit impact characteristics of scaled MLC NAND flash memories.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016
Proceedings of the 8th USENIX Workshop on Hot Topics in Storage and File Systems, 2016
Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory.
Proceedings of the 14th USENIX Conference on File and Storage Technologies, 2016
Proceedings of the 2016 International Conference on Embedded Software, 2016
Exploiting process variation for retention induced refresh minimization on flash memory.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Peak-to-average pumping efficiency improvement for charge pump in Phase Change Memories.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Computers, 2015
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Parallel Distributed Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
J. Parallel Distributed Comput., 2014
PUMA: Pseudo unified memory architecture for single-ISA heterogeneous multi-core systems.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014
Exploiting parallelism in I/O scheduling for access conflict minimization in flash-based solid state drives.
Proceedings of the IEEE 30th Symposium on Mass Storage Systems and Technologies, 2014
Combine thread with memory scheduling for maximizing performance in multi-core systems.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014
Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Exploit asymmetric error rates of cell states to improve the performance of flash memory storage systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh.
ACM Trans. Design Autom. Electr. Syst., 2013
Des. Autom. Embed. Syst., 2013
Coordinate page allocation and thread group for improving main memory power efficiency.
Proceedings of the Workshop on Power-Aware Computing and Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012
2011
Cooperating Write Buffer Cache and Virtual Memory Management for Flash Memory Based Systems.
Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011
Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache.
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011
Proceedings of the 11th International Conference on Embedded Software, 2011
2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010