Lu Jie

Orcid: 0000-0001-5046-3917

Affiliations:
  • Tsinghua University, Department of Electronic Engineering, Beijing, China
  • University of Michigan, Department of Electrical and Computer Engineering, Ann Arbor, MI, USA (PhD 2021)
  • Zhejiang University, Hangzhou, Zhejiang, China (former)


According to our database1, Lu Jie authored at least 24 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor.
IEEE J. Solid State Circuits, December, 2023

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 3.7mW 11b 1GS/s Time-Interleaved SAR ADC with Robust One-Stage Correlation-Based Background Timing-Skew Calibration.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 0.004mm<sup>2</sup> 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 0.014mm<sup>2</sup> 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A Fast Converging Correlation-Based Background Timing Skew Calibration Technique by Digital Windowing for Time-Interleaved ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 0.37mm<sup>2</sup> 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2<sup>nd</sup>-order Vector-Quantizer DEM.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM.
IEEE J. Solid State Circuits, 2021

10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension.
IEEE J. Solid State Circuits, 2020

9.4 A 4<sup>th</sup>-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC.
IEEE J. Solid State Circuits, 2019

Design Considerations for Integrated Radar Chirp Synthesizers.
IEEE Access, 2019

A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4<sup>th</sup>-Order Noise-Shaping SAR ADC.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017
A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process.
Sci. China Inf. Sci., 2017


  Loading...