Steven J. Koester

Orcid: 0000-0001-6104-1218

According to our database1, Steven J. Koester authored at least 18 papers between 2007 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to group-IV electronic and photonic devices".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
Supervised Learning in Temporally-Coded Spiking Neural Networks with Approximate Backpropagation.
CoRR, 2020

Spin-Hall MTJ Cells for Intra-Column Competition in Hierarchical Temporal Memory.
CoRR, 2020

SHE-MTJ Circuits for Convolutional Neural Networks.
CoRR, 2020

2019
Nonvolatile Spintronic Memory Cells for Neural Networks.
CoRR, 2019

Convolutional Neural Networks Utilizing Multifunctional Spin-Hall MTJ Neurons.
CoRR, 2019

Low Cost Hybrid Spin-CMOS Compressor for Stochastic Neural Networks.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Non-volatile Capacitance Tuning in Graphene/(Hf, Zr)O2/Metal Varactors.
Proceedings of the Device Research Conference, 2019

2018
Benchmarking Inverse Rashba-Edelstein Magnetoelectric Devices for Neuromorphic Computing.
CoRR, 2018

2017
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Glucose sensing with graphene varactors.
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016

Acetone sensing using graphene quantum capacitance varactors.
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016

2015
Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor.
Proc. IEEE, 2015

2014
Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs).
IEEE Trans. Very Large Scale Integr. Syst., 2013

2010
Practical Strategies for Power-Efficient Computing Technologies.
Proc. IEEE, 2010

2009
Low power circuit design based on heterojunction tunneling transistors (HETTs).
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008
Wafer-level 3D integration technology.
IBM J. Res. Dev., 2008

2007
Interconnects in the Third Dimension: Design Challenges for 3D ICs.
Proceedings of the 44th Design Automation Conference, 2007


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