Bruno Bougard

According to our database1, Bruno Bougard authored at least 55 papers between 2002 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Design, Implementation and Validation of a GNSS Measurement Exclusion and Weighting Function with a Dual Polarized Antenna.
Sensors, 2018

GNSS Measurement Exclusion and Weighting with a Dual Polarized Antenna: The FANTASTIC project.
Proceedings of the 8th International Conference on Localization and GNSS, 2018

2011
Energy Aware Signal Processing for Software Defined Radio Baseband Implementation.
J. Signal Process. Syst., 2011

2009
Energy-performance Exploration of a CGA-based SDR Processor.
J. Signal Process. Syst., 2009

Energy Aware Algorithm and Implementation of SDR Oriented HSDPA Chip Level Equalizer.
J. Signal Process. Syst., 2009

Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures.
IEEE Trans. Signal Process., 2009

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot.
Proc. IEEE, 2009

A System Level Algorithmic Approach toward Energy-Aware SDR Baseband Implementations.
Proceedings of IEEE International Conference on Communications, 2009

Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning.
Proceedings of the Design, Automation and Test in Europe, 2009

Finite precision processing in wireless applications.
Proceedings of the Design, Automation and Test in Europe, 2009

Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
MEERA: Cross-Layer Methodology for Energy Efficient Resource Allocation in Wireless Networks.
IEEE Trans. Wirel. Commun., 2008

Performance Analysis of Slotted Carrier Sense IEEE 802.15.4 Medium Access Layer.
IEEE Trans. Wirel. Commun., 2008

A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing.
IEEE Micro, 2008

Performance Analysis of Slotted Carrier Sense IEEE 802.15.4 Acknowledged Uplink Transmissions.
Proceedings of the WCNC 2008, IEEE Wireless Communications & Networking Conference, March 31 2008, 2008

Trade-off analysis of decoding algorithms and architectures for multi-standard LDPC decoder.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Application-driven adaptive fixed-point refinement for SDRs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

A unified instruction set programmable architecture for multi-standard advanced forward error correction.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures.
Proceedings of IEEE International Conference on Communications, 2008

Bridging the energy gap in size, weight and power constrained software defined radio: Agile baseband processing as a key enabler.
Proceedings of the IEEE International Conference on Acoustics, 2008

Adaptive SSFE Near-ML MIMO Detector with Dynamic Search Range and 80-103Mbps Flexible Implementation.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR Platform.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios.
Proceedings of the Design, Automation and Test in Europe, 2008

Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008

A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio.
Proceedings of the Design, Automation and Test in Europe, 2008

HOT TOPIC - 3D Integration or How to Scale in the 21st Century.
Proceedings of the Design, Automation and Test in Europe, 2008

How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach.
Proceedings of the 45th Design Automation Conference, 2008

2007
Green Reconfigurable Radio Systems.
IEEE Signal Process. Mag., 2007

<i>SmartMIMO</i>: An Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Next-Generation Wireless Local Area Networks.
EURASIP J. Wirel. Commun. Netw., 2007

A Wavelet-FFT Based Efficient Sparse OFDMA Demodulator and Its Implementation on VLIW Architecture.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Systematic Optimization of Programmable QRD Implementation for Multiple Application Scenarios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Efficient QRD for SRI-RLS Based Equalization on Programmable Architecture.
Proceedings of the IEEE International Conference on Acoustics, 2007

The Quality-Energy Scalable OFDMA Modulation for Low Power Transmitter and VLIW Processor Based Implementation.
Proceedings of the Global Communications Conference, 2007

Energy-efficient software-defined radio solutions for MIMO-based broadband communication.
Proceedings of the 15th European Signal Processing Conference, 2007

ESL design and HW/SW co-verification of high-end software defined radio platforms.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
Cross-layer power management in wireless networks and consequences on system-level architecture.
Signal Process., 2006

Subword-Parallel VLIW Architecture Exploration for Multimode Software Defined Radio.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Exploit Multiple-Domain Sparseness for HSDPA Chip Level Equalization in SDR: Algorithm and DSP Implementation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

SmartMIMO: Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Wireless Local Area Networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Quality-Energy Scalable Chip Level Equalization for HSDPA.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

Energy-scalable OFDM transmitter design and control.
Proceedings of the 43rd Design Automation Conference, 2006

A Scalable Baseband Platform for Energy-Efficient Reactive Software-Defined-Radio.
Proceedings of the 1st International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2006

2005
Energy Efficient Memory Architecture for High Speed Decoding of Block Turbo-Codes with the Fang-Buda Algorithm.
J. VLSI Signal Process., 2005

Optimizing Transmission and Shutdown for Energy-Efficient Real-time Packet Scheduling in Clustered Ad Hoc Networks.
EURASIP J. Wirel. Commun. Netw., 2005

Optimal fixed and scalable energy management for wireless networks.
Proceedings of the INFOCOM 2005. 24th Annual Joint Conference of the IEEE Computer and Communications Societies, 2005

Optimizing transmission and shutdown for energy-efficient packet scheduling in sensor networks.
Proceedings of the Wireless Sensor Networks, Second European Workshop, 2005

Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives.
Proceedings of the 2005 Design, 2005

From myth to methodology: cross-layer design for energy-efficient wireless communication.
Proceedings of the 42nd Design Automation Conference, 2005

2003
Memory Power Reduction for High-Speed Implementation of Turbo Codes.
J. VLSI Signal Process., 2003

2002
A class of power efficient VLSI architectures for high speed turbo-decoding.
Proceedings of the Global Telecommunications Conference, 2002

A 80 Mb/s low-power scalable turbo codec core.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002


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