Yong-Sung Cho

Orcid: 0000-0001-7505-823X

According to our database¹, Yong-Sung Cho authored at least 5 papers between 2012 and 2020.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2020

Convolutional-Neural-Network-Based Partial Discharge Diagnosis for Power Transformer Using UHF Sensor.

[BibT_eX]

[DOI]

IEEE Access, 2020

2017

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

2016

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

2012

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Yong-Sung Cho

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...