Yorgos Palaskas
Orcid: 0000-0003-0551-7327Affiliations:
- Intel Corporation, Hillsboro, OR, USA
- Columbia University, New York, NY, USA
According to our database1,
Yorgos Palaskas
authored at least 44 papers
between 2001 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2020
A Cellular Multiband DTC-Based Digital Polar Transmitter With -153-dBc/Hz Noise in 14-nm FinFET.
IEEE J. Solid State Circuits, 2020
Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A Cellular Multiband DTC-Based Digital Polar Transmitter With -153 dBc/Hz Noise in 14-nm FinFET.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2017
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2015
Proceedings of the 2015 IEEE International Conference on RFID, 2015
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement.
IEEE J. Solid State Circuits, 2012
A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS.
IEEE J. Solid State Circuits, 2012
A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application.
IEEE J. Solid State Circuits, 2011
Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2011
A 31.5dBm outphasing class-D power amplifier in 45nm CMOS with back-off efficiency enhancement by dynamic power control.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
A 12-element 60GHz CMOS phased array transmitter on LTCC package with integrated antennas.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving.
IEEE J. Solid State Circuits, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
IEEE J. Solid State Circuits, 2009
A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process.
IEEE J. Solid State Circuits, 2006
A 5-GHz 108-Mb/s 2 $\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${\rm P}_{\rm 1dB}$ Power Amplifiers in 90-nm CMOS.
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
A "divide and conquer" technique for implementing wide dynamic range continuous-time filters.
IEEE J. Solid State Circuits, 2004
2003
Dynamic range optimization of weakly nonlinear, fully balanced, Gm-C filters with power dissipation constraints.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A power efficient channel selection filter/coarse AGC with no range switching transients.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Design considerations and experimental evaluation of a syllabic companding audio frequency filter.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A "divide and conquer" technique for the design of wide dynamic range continuous time filters.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001