Alessio Carpegna

CoRR, 2024

2023

NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.

[BibT_eX]

[DOI]

CoRR, 2023

Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies.

[BibT_eX]

[DOI]

Fabio Pavanello

Elena Ioana Vatajelu

Alberto Bosio

Thomas Van Vaerenbergh

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

Micro-Architectural features as soft-error markers in embedded safety-critical systems: preliminary study.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

2022

Fast Exploration of the Impact of Precision Reduction on Spiking Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2022

Are micro-architectural features able to explain faulty executions in the presence of soft errors? A preliminary study.

[BibT_eX]

[DOI]

CoRR, 2022

FPGA-optimized Hardware acceleration for Spiking Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2022

Prediction of the Impact of Approximate Computing on Spiking Neural Networks via Interval Arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Artificial Resilience in neuromorphic systems.

[BibT_eX]

[DOI]